ADC-321 Datasheet, PDF (4/8 Pages) List of Unclassifed Manufacturers – 8-Bit, 50MHz Video A/D Converter

THEORY OF OPERATION
(See Functional Block Diagram, Figure 1, and Timing
Diagrams, Figure 2)
1. The DATEL ADC-321 is a 2-step parallel A/D converter
featuring a 4-bit upper comparator group and two 4-bit
lower comparator groups, each with built-in sample and
hold. A reference voltage equal to the voltage between
(VRT – VRB)/16 is constantly applied to the 4-bit upper
comparator block. A voltage corresponding to the upper
data is fed through the reference supply to the lower data.
VRTS and VRBS pins provde the self generation function for
VRT (reference voltage top) and VRB (reference voltage
bottom) voltages.
2. This converter uses an offset cancelation type comparator
and operates synchronously with the external clock. It
features various operating modes which are shown in the
Timing Diagram (Figure 2) by the symbols S, H and C.
These characters stand for Input Sampling (Auto Zero)
Mode, Input Hold Mode and Comparison Mode.
3. The operation of the respective parts is as indicated in
Figure 2-3. For instance, input voltage N is sampled with
the falling edge of the first clock by means of the upper
ADC-321
8-Bit, 50MHz Video A/D Converter
comparator block and the lower comparator A block. Input
voltage N+1 is sampled with the falling edge of the second
clock by means of the upper comparator block and lower
comparator B block. The upper comparator block finalizes
comparison data UD(N) with the rising edge of the second
clock. The lower comparator block finalizes comparison
data LD(N) with the rising edge of the third clock. UD(N)
and LD(N) are combined and routed to the output as Output
Data N with the rising edge of the fourth clock. Thus there
is a 2.5 clock delay from the analog input sampling point to
the digital data output.
Table 2: Digital Output Coding
VIN
0V
+7.812mV
OUTPUT CODE
MSB
LSB
0000
0000
0000
0001
+0.9922V
+1.000V
0111
1000
1111
0000
+1.500V
1100
0000
+1.9922V
1111
1111
tr = 4.5ns
OE INPUT
1.3V
OUTPUT 1
OUTPUT 2
tplz
10%
tphz
90%
tr = 4.5ns
90%
10%
tpzl
1.3V
tpzh
1.3V
Figure 2-1. ADC-321 Timing Diagram
3V
0V
VOH
VOL /(=DGND)
VOH/(=DGND)
VOL
tr = 4ns tf = 4ns
3V
90%
CLOCK 1.3V
10%
0V
DATA ^{0. 7 DVS}
OUTPUTS
0. 3 DVS
tpLH
tpHL
Figure 2-2. ADC-321 Timing Diagram
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MDA_ADC-321.B01 Page 4 of 8