ADC-321 Datasheet, PDF (1/8 Pages) List of Unclassifed Manufacturers – 8-Bit, 50MHz Video A/D Converter

ADC-321
8-Bit, 50MHz Video A/D Converter
OBSOLETE PRODUCT
FEATURES
Contact Factory for Replacement Model
Low power dissipation (180mW max.)
Input signal bandwith (100MHz)
Optional synchronized clamp function
Low input capacitance (15pF typ.)
+5V or +5V /+3.3V power supply operation
Differential nonlinearity (±½LSB max.)
Optional self-biased reference
CMOS/TTL compatible inputs
Outputs 3-state TTL compatible
Surface mount package
PRODUCT OVERVIEW
The ADC-321 is an 8-bit, high speed, monolithic CMOS, sub-ranging
A/D converter. The ADC-321 achieves a sampling rate comparable to flash
converters by employing a sub-ran single +5V or dual +5V and +3.3V
power source to allow easy interfacing with 3.3V logic.
An optional synchronous clamp function useful for video signal
processing is provided. The ADC-321 is well suited for the portable video
signal processors due to its low 125mW typical power dissipation. The
ADC-321 also features ±0.5 LSB max. differential non-linearity, a self bias
function that can eliminate the need for external references, SNR with THD
of 45dB, a small 32-pin QFP package and an operating temperature range
of –40 to +85°C
INPUT/OUTPUT CONNECTIONS
Pin
Function
Pin
1
BIT 8 (LSB)
32
2
BIT 7
31
3
BIT 6
30
4
BIT 5
29
5
BIT 4
28
6
BIT 3
27
7
BIT 2
26
8
BIT 1 (MSB)
25
9
TEST
24
10
+DVS (Digital)
23
11
TEST
22
12
A/D CLOCK
21
13
NO CONNECTION
20
14
NO CONNECTION
19
15
CLAMP IN (CLP)
18
16
+AVS (Analog)
17
Function
NO CONNECTION
DIGITAL GROUND (DGND)
OUTPUT ENABLE (OE)
CLAMP ENABLE (CLE)
DIGITAL GROUND (DGND)
CLAMP CONTROL (COP)
CLAMP REF. (VREF)
REF. BOTTOM SENSE (VRBS)
REF. BOTTOM (VRB)
ANALOG GROUND (AGND)
ANALOG GROUND (AGND)
ANALOG IN (VIN)
+AVS (Analog)
+AVS (Analog)
REF. TOP (VRT)
REF. TOP SENSE (VRTS)
+AVS 16
VRTS 17
VRT 18
+AVS 19
+AVS 20
VIN 21
AGND 22
AGND 23
VRB 24
VRBS 25
VREF 26
DGND 28
Ḥ
CLAMP CONTROL 27
CLAMP ENABLE 29
For full details go to
www.murata-ps.com/rohs
Reference
Supply
Clock
Generator
–
+
A
4-Bit
Lower
Sampling
Comparator
B
A
4-Bit
Lower
Encoder
B
Lower
Data
Latch
30 OUTPUT ENABLE
31 DGND
1 BIT 8 (LSB)
2 BIT 7
3 BIT 6
4 BIT 5
4-Bit
Upper
Sampling
Comparator
4-Bit
Upper
Encoder
D-FF
Upper
Data
Latch
5 BIT 4
6 BIT 3
7 BIT 2
8 BIT 1 (MSB)
12 A/D CLOCK
15 CLAMP IN
9 TEST (Open)
10 +DVS
11 TEST (Open)
wwFwig.umre 1u. rAaDCt-a32-1pFsu.nccotiomnal Block DiagraTmechnical enquiries email: [e-mail], tel: [phone]
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