D1U86 Datasheet, PDF (3/7 Pages) Murata Power Solutions Inc. – 86mm 1U Front End DC-DC Power Supply Converter

D1U86-D-1600-12-HBxDC Series
86mm 1U Front End DC-DC Power Supply Converter
OUTPUT CONNECTOR AND SIGNAL SPECIFICATION
EMISSIONS AND IMMUNITY
Characteristic
Standard
Conducted Emissions
FCC 47 CFR Part 15/CISPR 22/EN55022
ESD Immunity
IEC/EN 61000-4-2
Radiated Field Immunity
IEC/EN 61000-4-3
Electrical Fast Transient Immunity
IEC/EN 61000-4-4
Surge Immunity
IEC/EN 61000-4-5
Radiated Field Conducted Immunity
IEC/EN 61000-4-6
Magnetic Field Immunity
IEC/EN 61000-4-8
Compliance
Class A, 6dB margin
Level 3 criteria A
Level 3 criteria B
Level 3 criteria A
Level 2 criteria B
Level 3 criteria A
3 A/m criteria B
STATUS AND CONTROL SIGNALS
Signal Name
I/O Description
PSOK (Output OK)
Output The PSOK output is a logical “OR” of three internal signals; however the output is not strictly a
“digital” signal that transitions between “low” and “high” but is analogue in nature. The internal
logic signals are as follows:
1. DC_OK_H
2. PWR_GOOD_H
3. PS_FAULT_L
The following is a “truth table” that shows the analogue levels of operation of the signal dependent
upon the three internal logic signals:
PSOK TRUTH TABLE VS. ANALOG OUTPUT
DC_OK_H PWR_GOOD_H PS_FAULT_L
PSOK
OPERATION
MODE
0
0
1
< 0.1Vdc
No DC Input
0
1
1
(1/3) VDD
Invalid
1
0
1
(2/3) VDD VDD = 3.3Vdc Standby
1
1
1
VDD
Power Good
X
X
0
0.2-0.4Vdc
PS Fault
The timing relationship of this signal is shown in the Timing Specification section that follows.
PS_INTERRUPT
(FAULT/WARNING)
PRESENT#
Output
Output
The signal output is driven low to indicate that the power supply has detected a warning or fault and
is intended to alert the system. This output must be driven high when the power is operating
correctly (within specified limits).
The signal will revert to a high level when the warning/fault stimulus (that caused the alert) is
removed.
Based on the industry standard Common Slot requirement this signal is used to detect the presence
of an (installed) power module within the host system. However it is also intended to “Enable” the
Main 12Vdc output.
The signal is also designed to control the power module during hot plug insertion/extraction in
conjunction with the host system and is provided on a short “last to make; first to break” signal pin.
To “enable” the Main 12Vdc output the signal requires to be pulled “high” with respect +12V_GND.
The value of the pull up resistor varies with the applied voltage rail and is as follows:
1. If the signal is to be pulled up to the 12VSB output then the resistor value should be 21KΩ
2. If the signal is to be pulled up to a 3.3Vdc rail (locally derived within the host system) then the
resistor value should be 5.11KΩ
PS_ON
(Power Supply
Enable/Disable
Input The PS_ON can be permanently connected to +12V_GND (via the host system mid/back plane) to
“enable” the Main 12Vdc output.
Alternatively the signal can be connected via the host system electronics to provide the ability to
switch between “enable/disable” states.
The signal is pulled up internally to the internal housekeeping supply (within the power supply). The
power supply main 12Vdc output will be enabled when this signal is pulled low to +12V_GND.
In the low state the signal input shall source a nominal 1.2mAdc.
The 12Vdc output will be disabled when the input is driven higher than 2.4V, or open circuited.
Cycling this signal shall clear latched fault conditions.
Interface Details
Each internal signal is buffered and
provided with a series or pull up
resistor:
1. DC_OK_H; 1K62 series resistor
2. PWR_GOOD_H; 3K32 series
resistor
3. PS_FAULT_L; a 10K pull up
resistor to VDD_OR (an internally
derived 3.3VDC rail)
The embedded truth table shows the
appropriate levels.
Pulled up internally via 10K to 3.3Vdc.
A logic high >2.0Vdc
A logic low <0.8Vdc
Driven low by internal buffer (open
drain output).
The voltage level on the system side
of the PSPRESENT# signal will be as
follows:
1. When the power module is not
installed the voltage will be as per
the rail to which it is pulled up to
(3.3Vdc or 12Vdc)
2. When the power module is
installed the voltage will be pulled
down to 0.54Vdc ±5%).
Pulled up internally via 10K to 3.3Vdc.
A logic high >2.0Vdc
A logic low <0.8Vdc
Input is via CMOS Schmitt trigger
buffer.
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D1U86-D-1600-12-HBxDC.A02 Page 3 of 7