MP2932GQK-LF-Z Datasheet, PDF(13/23 Page) MPS Industries, Inc. – 6-Phase PWM Controller with 8-Bit DAC Code for VR10 and VR11

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MP2932GQK-LF-Z Datasheet, PDF (13/23 Pages) MPS Industries, Inc. – 6-Phase PWM Controller with 8-Bit DAC Code for VR10 and VR11

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MP2932 - 6-PHASE PWM CONTROLLER WITH 8-BIT ADC CODE

Soft-Start

MP2932 has 4 periods during soft-start as

shown in Figure 7. After VCC, EN_VTT and

EN_PWR reach their POR/enable thresholds,

the controller will have fixed delay period td1

1.36ms. After the delay period, the VR will

begin first soft-start ramp until the output

voltage reaches 1.1V. Then, the controller will

regulate the VR voltage at 1.1V for another

fixed period td3. At the end of td3 period, MP2932

reads the ID signals. If the ID code is valid,

MP2932 will initiate the second soft-start ramp

until the voltage reaches the ID voltage minus

offset voltage.

1.1V

VOUT

EN_VTT

td1

td2

td3 td4 td5

VR_RDY

500us/DIV

Figure 7âSoft-Start Waveforms

The soft-start time is the sum of the 4 periods,

as shown in Equation (11):

tSS ï½ td1 ï« td2 ï« td3 ï« td4

(11)

td1 is about 1.36ms. td3 is determined by the

fixed 85Âµs plus the time to obtain valid ID

voltage. If the ID is valid before the output

reaches the 1.1V, the minimum time to validate

the ID input is 500ns. Therefore the minimum

td3 is about 86Âµs.

During td2 and td4, MP2932 digitally controls the

DAC voltage change at 6.25mV per step. The

time for each step is determined by the

frequency of the soft-start oscillator which is

defined by the resistor RSS from SS pin to GND.

The second soft-start ramp time td2 and td4 can

be calculated based on Equations (12) and (13):

t d2

ï½

ï´

1.1ï´ RSS

6.25 ï´ 25

(us)

(12)

ï¨ ï© td4

ï½

2ï´

VVID ï 1.1 ï´ RSS

6.25 ï´ 25

(us)

(13)

For example, when ID is set to 1.5V and the

RSS is set at 100kâ¦, the first soft-start ramp time

td2 will be 469Âµs and the second soft-start ramp

time td4 will be 171Âµs.

After the DAC voltage reaches the final ID

setting, VR_RDY will be set to high with the

fixed delay td5, itâs about 85Âµs.

VR_RDY Signal

The VR_RDY pin is an open-drain logic output.

It is pulled low during shutdown and releases

high after a successful soft-start. VR_RDY will

be pulled low when an under-voltage or over-

voltage condition is detected, or the controller is

disabled by a reset from EN_PWR, EN_VTT,

POR, or ID OFF-code.

Under-voltage Detection

The under-voltage threshold is set at 50% of

the ID code. When the output voltage at VSEN

is below the under-voltage threshold, VR_RDY

is pulled low.

Over-voltage Protection (OVP)

Regardless of the VR being enabled or not, the

MP2932 OVP circuit will be active after its POR.

The OVP thresholds are different at different

operation conditions. When VR is not enabled

and during the soft-start intervals td1, td2 and td3,

the OVP threshold is 1.275V. Once the

controller detects valid ID input, the OVP trip

point will be changed to DAC + 175mV.

VR_RDY

50%

DAC

VDIFF

SOFT-START, FAULT

AND CONTROL LOGIC

85uA

IAVG

VID + 0.175V

Figure 8âVR_RDY and Protection Circuitry

MP2932 Rev.1.02

www.MonolithicPower.com

4/30/2012

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

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