MP2932GQK-LF-Z Datasheet, PDF (11/23 Pages) MPS Industries, Inc. – 6-Phase PWM Controller with 8-Bit DAC Code for VR10 and VR11

MP2932 - 6-PHASE PWM CONTROLLER WITH 8-BIT ADC CODE
If the RC network components are selected
such that the RC time constant (=R*C) matches
the inductor time constant (=L/DCR), the
voltage across the capacitor V_C is equal to the
voltage drop across the DCR, i.e., proportional
to the channel current.
Therefore, the current out of ISEN+ pin (I_SEN), is
proportional to the inductor current and it can
be seen form Equation (4).
ISEN

IL

DCR
RISEN
(4)
Resistive Sensing
For accurate current sense, a current-sense
resistor R_SENSE in series with each output
inductor can also be adopted (see Figure 3).
This technique reduces overall converter
efficiency due to the additional power loss on
R_SENSE.
Equation (5) shows the relationship between
the channel current to the sensed current I_SEN.
ISEN

IL

RSENSE
RISEN
(5)
I_L
L
R_{SENSE VOUT}
MP2932 INTERNAL CIRCUIT
C_OUT
In
R_{I SEN (n)}
CURRENT
SENSE
I_SEN
=I_L
R_SENSE
R_ISEN
ISEN-(n)
ISEN+(n)
C_T
Figure 3—Sense Resistor in Series with
Inductors
Channel-Current Balance
The sensed current from each active channel is
summed together and divided by the number of
active channels. The resulting average current
(I_AVG) provides a measure of the total load
current. Channel current balance is achieved by
comparing the sensed current of each channel
to the average current to make an appropriate
adjustment to the PWM duty cycle of each
channel.
Output Voltage and Load-Line Regulation
The MP2932 uses an internal differential
remote-sense amplifier as shown in Figure 4.
The microprocessor voltage is sensed between
the VSEN and RGND pins.
The output of the error amplifier (V_COMP) is
compared to sawtooth waveforms to generate
the PWM signals. The typical open-loop gain of
error amplifier is no less than 80dB, and the
typical open-loop bandwidth is no less than
20MHz. The PWM signals control the timing of
the MPS Intelli-phase and regulate the
converter output to the specified reference
voltage.
EXTERNAL CIRCUIT
COMP
R_C CC _DAC
R_REF
REF
C_REF
R _FB
FB
IDROOP
V_DROOP
VDIFF
MP2932 INTERNAL CIRCUIT
I_AVG
V_COMP
ERROR AMPLIFIER
V_OUT+
VSEN
V_OUT-
RGND
DIFFERENTIAL
REMOTE -SENSE
AMPLIFIER
Figure 4—Output Voltage and Load-line
Regulation
The load-line is realized by a resistor R_FB
connected between FB pin and the remote
sense output (VDIFF). As shown in Figure 4,
the average current of all active channels (I_AVG)
flows from FB through the load-line regulation
resistor R_FB. The resulting voltage drop across
R_FB can be seen form Equation (6):
VDROOP  IAVGRFB
(6)
The output voltage is reduced by the droop
voltage V_DROOP, and it is a function a load
current. It’s derived by combining Equation (6)
with the appropriate sensing current expression
defined by the current sense method.
MP2932 Rev.1.02
www.MonolithicPower.com
11
4/30/2012
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