NB669 Datasheet, PDF (13/19 Pages) Monolithic Power Systems – 24V, High Current Synchronous Buck Converter With LDO

NB669, 24V, HIGH CURRENT SYNCHRONOUS BUCK CONVERTER WITH LDO
CLK
100nF
100nF
5V
12V/100mA
100nF
100nF
100nF
PGND
PGND
PGND
Figure 7—Charge Pump Circuit
Power Good (PG)
The NB669 has power-good (PG) output used to
indicate whether the output voltage of the Buck
regulator is ready or not. The PG pin is the open
drain of a MOSFET. It should be connected to
V_CC or other voltage source through a resistor
(e.g. 100k). After the input voltage is applied, the
MOSFET is turned on so that the PG pin is pulled
to GND before SS is ready. After FB voltage
reaches 95% of REF voltage, the PG pin is
pulled high after a delay. The PG delay time is
0.5ms.
When the FB voltage drops to 85% of REF
voltage, the PG pin will be pulled low.
Over Current Protection
NB669 has cycle-by-cycle over current limiting
control. The current-limit circuit employs a
"valley" current-sensing algorithm. The part uses
the Rds(on) of the low side MOSFET as a
current-sensing element. If the magnitude of the
current-sense signal is above the current-limit
threshold, the PWM is not allowed to initiate a
new cycle.
The trip level is fixed internally. The inductor
current is monitored by the voltage between GND
pin and SW pin. GND is used as the positive
current sensing node so that GND should be
connected to the source terminal of the bottom
MOSFET.
Since the comparison is done during the high
side MOSFET OFF and low side MOSFET ON
state, the OC trip level sets the valley level of the
inductor current. Thus, the load current at over-
current threshold, I_OC, can be calculated as
follows:
I_OC
= I _ limit
+
ΔI_inductor
2
(6)
In an over-current condition, the current to the
load exceeds the current to the output capacitor;
thus the output voltage tends to fall off.
Eventually, it will end up with crossing the under
voltage protection threshold and shutdown.
Over/Under-Voltage Protection (OVP/UVP)
NB669 monitors output voltage to detect over
and under voltage. When the feedback voltage
becomes higher than 115% of the target voltage,
the controller will enter Dynamic Regulation
Period. During this period, the LS will off when
the LS current goes to -1A, this will then
discharge the output and try to keep it within the
normal range. If the dynamic regulation can not
limit the increasing of the Vo, once the feedback
voltage becomes higher than 130% of the
feedback voltage, the OVP comparator output
goes high and the circuit latches as the high-side
MOSFET driver OFF and the low-side MOSFET
driver turn on acting as an -1A current source.
When the feedback voltage becomes lower than
60% of the target voltage, the UVP comparator
output goes high if the UV still occurs after 26us
delay; then the fault latch will be triggered---
latches HS off and LS on; the LS FET keeps on
until the inductor current goes zero.
UVLO Protection
The NB669 has under-voltage lock-out protection
(UVLO). When the VCC voltage is higher than
the UVLO rising threshold voltage, the part will
be powered up. It shuts off when the VIN voltage
is lower than the UVLO falling threshold voltage.
This is non-latch protection. The part is disabled
when the VCC voltage falls below 4.65V. If an
application requires a higher under-voltage
lockout (UVLO), use the EN pin as shown in
Figure 8 to adjust the input voltage UVLO by
using two external resistors. It is recommended
to use the enable resistors to set the UVLO
falling threshold (VSTOP) above 4.65V. The
rising threshold (VSTART) should be set to
provide enough hysteresis to allow for any input
supply variations.
NB669 Rev. 1.01
www.MonolithicPower.com
13
7/23/2013
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.