MC44461 Datasheet, PDF (9/16 Pages) Motorola, Inc – PICTURE–IN–PICTURE (PIP) CONTROLLER

MC44461
PIN FUNCTION DESCRIPTION (continued)
Pin
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{54, 53, 52,}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{42, 41, 40}
Equivalent Internal Circuit
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _0.01
Description
Encoder and Decoder YUV Caps
During the internal H rate clamping time the YUV reference levels are
set by the charge on the capacitors attached to these pins. The
nominal value of these capacitors should be 0.01 µF.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{Pins 11 to 13, 16 to 27, 55 and 56 are test pins configured as outputs in a high impedance state. In an application, no connection should be made to these pins.}
SOFTWARE CONTROL OF THE MC44461
Communications to and from the MC44461 follows the I2C
interface protocol defined by the Philips Corporation. In
simple terms, the I2C is a two line, multi–master, bidirectional
bus used for data transfer. Although an I2C system can be
multi–master, the MC44461 never functions as a master.
The MC44461 has a write address of $24 and a flag read
address of $25. A block diagram of the I2C interface is shown
in Figure 3. Writing to the MC44461 registers can cause
momentary jitter or other undesirable effects to the TV
screen, writing should be done only during the vertical
retrace (before line 20).
Write to Control Registers
A write cycle consists of three bytes, with three
acknowledge bits.
1) The first byte is always the write address for the
MC44461 ($24).
2) The second byte defines the sub–address register,
within the MC44461, to be updated; $00 through $0B.
3) The third byte is the data for that register.
The communication begins when a start sequence (data
line taken low while the clock line is high) is initiated by the
master (MCU) and detected by the MC44461, generating an
internal reset. The first byte is then generated, and if the
address is correct ($24), an acknowledge is generated by the
MC44461, which tells the master to continue to send data.
The second byte is then entered, followed by an
acknowledge. The third byte is the operative data which is
stored in the designated register, followed by the third
acknowledge. Writing to multiple registers in a single write
operation is permitted in the MC44461. The sub–address is
auto–incremented while receiving n – data bytes + Ack,
ending with the stop sequence. The sub–address of the 11
registers are at $00 through $0B.
Clock
Data
5
6
Acknowledge
Figure 3. I2C Bus Interface and Decoder
Start Bit
Recognition
Reset
Clock Counter
8–Bit Shift Register
Chip
Address
Latch
Read/
Write
Latch
19 Registers
Flag Data
Sub–Address
Latches
MOTOROLA ANALOG IC DEVICE DATA
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