MC44461 Datasheet, PDF (10/16 Pages) Motorola, Inc – PICTURE–IN–PICTURE (PIP) CONTROLLER

MC44461
Figure 4. I2C Data Transfer
SDA
MSB
SCL
1
2
7
8
9
ACK
MSB
1
2
7
8
9
ACK
Start
Condition
Stop
Condition
S
Slave Address
R/W
A Sub–Address A
Data A P
A = Acknowledge
S = Start
P = Stop
Data Transferred
(n Bytes + Acknowledge)
I2C REGISTER DESCRIPTIONS
Base write address = 24h
Base read address = 25h
Read Register
There are two active bits in the single read byte available
from the MC44461 as follows:
Write Vertical Indicator (WVI0) – D7
When 0 indicates that the write operation specified by the
last I2C command has been completed.
PIP Sync Detect Bit (PSD0) – D1
When 0 indicates that the PIP video H pulses are present
and the horizontal timebase oscillator is within acceptable
limits.
Write Registers
Read Start Position/Write Start Position Registers
Sub–address = 00h
Write Raster Position Start Bits (WPS0–2) – D0–D2
Establishes the horizontal beginning of the PIP and its
black level measurement gate. This beginning may be varied
by approximately 3.0 µs. The position of this pulse may be
observed through the Multi Test Pin 30 (See Test Mode
Register Sub–address 03h).
Read Raster Position Bits (RPS0–3) – D4–D7
Establishes the clamp gate position for the black level
reference for the main picture. This position may be varied by
approximately 5.0 µs. The position of this pulse may be
observed through the Multi Test Pin 30 (See Test Mode
Register Sub–address 03h).
Pip Switch Delay/Vertical Filter Register
Sub–address = 01h
PIP Switch Delay Bits (PSD0–3) – D0–D3
Delays the start of PIP on time relative to the PIP picture.
These bits are used to center the PIP border and PIP picture
in the horizontal direction.
Vertical Filter Bit (VFON) – D4
When the filter is activated (VFON = 1) a three line
weighted average is taken to provide the data stored in the
field memory.
Border Color Register
Sub–address = 02h
Border Color Bits (BC0–2) – D0–D2
These Bits control the color of the border. Note that when
using one of the saturated border colors it is possible to get
objectionable dot crawl at the edge of the border in some TVs
unless appropriate comb filtering is used in the TV circuitry.
BC (2:0)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₀₀₀
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₀₀₁
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₀₁₀
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₀₁₁
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₁₀₀
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₁₀₁
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₁₁₀
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₁₁₁
Border Color
Black
White 70%
No Border (clear)
No Border (clear)
Blue
Green
Red
White
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{Test Mode/Main Vertical and Horizontal Polarity Register}
Sub–address = 03h
Internal Test Mode Register (ITM0–2) – D0–D2
Sets the Multi Test Pin output to provide one of several
internal signals for test and production alignment. Also
controls the test memory address counter.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{ITM (2:0)}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₀₀₀
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₀₀₁
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₀₁₀
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₀₁₁
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₁₀₀
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₁₀₁
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₁₁₀
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₁₁₁
Multi–Test I/O and Function
Input – Analog Test mode
Input – Digital Test mode
Output – Sync Detect
Output – PIP Switch
Output – PIP H Detect
Output – PIP V Detect
Output – PIP Clamp
Output – Main Clamp
10
MOTOROLA ANALOG IC DEVICE DATA