68HC05PD6 Datasheet, PDF (81/165 Pages) Motorola, Inc – SPECIFICATION (General Release)

July 7, 1997
GENERAL RELEASE SPECIFICATION
Internal
Processor Clock
T00
Internal
T01
Timer
Clocks
T10
T11
Counter(16 Bit) _{$FFEB $FFEC}
Input
Edge
note
Internal Capture Latch
Capture
Register
$????
Input Capture
Flag (ICF)
$FFED
$FFEE $FFEF
$FFED
NOTE: If the input edge occurs in the shaded area from one timer state T10 to
the other timer state T10 the input capture flag is set during the next state
T11.
Figure 9-6. Timer State Timing Diagram For Input Capture
MC68HC05PD6
REV 1.1
TIMER SYSTEM
MOTOROLA
9-9