68HC05PD6 Datasheet, PDF (114/165 Pages) Motorola, Inc – SPECIFICATION (General Release)

GENERAL RELEASE SPECIFICATION
July 7, 1997
be set, but not the framing error bit, and the byte will not be transferred to the
serial communications data register. The FE bit is cleared when the serial
communications status register is accessed (with FE set) followed by a read of
the serial communications data register. Reset clears the FE bit.
11.9.5 Baud Rate Register
7
R
0
SCBRR
$000A ^W
reset
0
6
5
4
3
2
1
0
0
0
SCP1
SCP0
SCR2
SCR1
SCR0
0
0
0
0
U
U
U
The baud rate register provides the means for selecting different baud rates which
may be used as the rate control for the transmitter and receiver. The SCP0-SCP1
bits function as a prescaler for the SCR0-SCR2 bits. Together, these five bits
provide multiple, baud rate combinations for a given internal processor clock
frequency.
SCP0, SCP1
These two bits in the baud rate register are used as a prescaler to increase the
range of standard baud rates controlled by the SCR0-SCR2 bits. A table of the
prescaler internal processor clock division versus bit levels is provided below.
Reset clears SCP1-SCP0 bit (divide-by-one).
SCP1
0
0
1
1
SCP0
0
1
0
1
INTERNAL PROCESSOR CLOCK
DIVIDE BY
1
3
4
13
SCR2, SCR1, SCR0
These three bits in the baud rate register are used to select the baud rates of
both the transmitter and receiver. A table of baud rates versus bit levels is
shown below. Reset does not affect the SCR2-SCR0 bits.
The diagram of Figure 11-7 and Table 11-1 and Table 11-2 illustrate the divided
chain used to obtain the baud rate clock (transmit clock). Note that there is a fixed
rate divide-by-16 between the receive clock (RT) and the transmit clock (Tx). The
actual divider chain is controlled by the combined SCP0-SCP1 and SCR0-SCR2
bits in the baud rate register as illustrated. All divided frequencies shown in the
first table represent the final transmit clock (the actual baud rate) resulting from
the internal processor clock division shown in the “divide-by” column only
MOTOROLA
11-12
SERIAL COMMUNICATIONS INTERFACE
MC68HC05PD6
REV 1.1