MCM67Q909 Datasheet, PDF (8/10 Pages) Motorola, Inc – 512K x 9 Bit Separate I/O Synchronous Fast Static RAM

BOUNDARY SCAN CYCLE TIMING
MCM67Q909–12
Parameter
Symbol
Min
Max
Cycle Time
tCHCH2
100
—
Clock High Pulse Width
Clock Low Pulse Width
Scan Mode Setup Time
tCHCL2
40
—
tCLCH2
40
—
tSS
10
—
Bypass Mode Setup Time
Scan Mode Recovery Time
SCK Low to SE Hold High
tBS
10
—
tSR
100
—
tCLMH
10
—
SE High to SCK High Setup
SCK High to SE Low Hold Time
tMHCH
10
—
tCHML
10
—
SDI Valid to SCK High Setup
tIVCH
10
—
SCK High to SDI Don’t Care
tCHIX
10
—
SCK Low to SDO Valid
tCLOV
—
20
NOTES:
1. The minimum delay required between ending normal operation and beginning scan operations.
2. The minimum delay required between ending shift mode and beginning bypass mode.
3. The minimum delay required before restarting normal RAM operation.
4. The minimum delay required before executing a parallel load operation.
5. The minimum delay required between a parallel load operation and a shift.
6. Minimum shift command hold time.
Unit Notes
ns
ns
ns
ns
1
ns
2
ns
3
ns
4
ns
5
ns
6
ns
ns
ns
BOUNDARY SCAN
OVERVIEW
Boundary scan is a simple, non–intrusive scheme that
allows verification of electrical continuity for each of a
clocked RAMs logically active inputs and I/Os without ad-
versely affecting RAM performance. Boundary scan allows
the user to monitor the logic levels applied to each signal I/O
on the RAM, and to shift them out in a serial bit stream.
OPERATION
Boundary scan requires four signal pins for implementa-
tion: scan data in (SDI), scan data out (SDO), scan clock
(SCK, active high), and scan enable (SE, active high).
Boundary scan provides three modes of operation: (1) nor-
mal RAM operation, (2) scan, and (3) bypass. For normal
RAM operation, SCK and SE must be held low. The RAM will
always return to normal operation immediately after the RAM
receives a rising edge of the RAM input clock (K) with SCK
and SE held low. To enter scan mode, SCK is activated. The
first rising edge of SCK is used to latch in the data on the
scan registers. SE is then driven high to disable additional in-
put data from entering the scan registers. Every falling edge
of SCK serially shifts data through the scan registers and
onto the SDO pin. To enter bypass mode, simply exercise
SCK with SE held low. In this mode, SDI is sampled on the
rising edge of SCK. The level found on SDI is then driven out
on SDO on the next falling edge of SCK.
MCM67Q909
8
MOTOROLA FAST SRAM