MCM67Q909 Datasheet, PDF (1/10 Pages) Motorola, Inc – 512K x 9 Bit Separate I/O Synchronous Fast Static RAM

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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Advance Information
512K x 9 Bit Separate I/O
Synchronous Fast Static RAM
MCM67Q909
The MCM67Q909 is a 4M–bit static random access memory, organized as
512K words of 9 bits. It features separate TTL input and output buffers, which
drive 3.3 V output levels, and incorporates input and output registers on–board
with high speed SRAM. It also features transparent–write and data pass–through
capabilities.
The synchronous design allows for precise cycle control with the use of an
external single clock (K). The addresses (A0 – A18), data input (D0 – D8), data
output (Q0 – Q8), write–enable (W), chip–enable (E), and output–enable (G), are
registered on the rising edge of clock (K).
The control pins (E, W, G) function differently in comparison to most synchro-
nous SRAMs. This device will not deselect with E high. The RAM remains active
at all times. If E is registered high, the output pins (Q0 – Q8) will be driven if G
is registered low. The transparent write feature allows the output data to track the
input data. E, G, and W must be asserted to perform a transparent write (write
and pass–through). The input data is available at the ouputs on the next rising
edge of clock (K).
The pass–through function is always enabled. E high disables the write to the
array while allowing a pass–through cycle to occur on the next rising edge of
clock (K). Only a registered G high will three–state the outputs.
The MCM67Q909 is available in an 86–bump surface mount PBGA (Plastic
Ball Grid Array) package.
86 BUMP PBGA
CASE 896A–02
PIN NAMES
A0 – A18 . . . . . . . . . . . . . . . . . Address Input
E . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable
W . . . . . . . . . . . . . . . . . . . . . . . . Write Enable
G . . . . . . . . . . . . . . . . . . . . . . Output Enable
D0 – D8 . . . . . . . . . . . . . . . . . . . . Data Inputs
Q0 – Q8 . . . . . . . . . . . . . . . . . . Data Outputs
K . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Input
SCK . . . . . . . . . . . . . . . . . . Scan Clock Input
SE . . . . . . . . . . . . . . . . . . . . . . . Scan Enable
SDI . . . . . . . . . . . . . . . . . . . . Scan Data Input
SDO . . . . . . . . . . . . . . . . . Scan Data Output
VCC . . . . . . . . . . . . . . . + 5 V Power Supply
VSS . . . . . . . . . . . . . . . . . . . . . . . . . . Ground
NC . . . . . . . . . . . . . . . . . . . . . No Connection
• Single 5 V ± 5% Power Supply
• Fast Cycle Time: 12 ns Max
• Single Clock Operation
• TTL Input and Output Levels (Outputs LVTTL Compatible)
• Address, Data Input, E, W, and G Registers On–Chip
• 83 MHz Maximum Clock Cycle Time
• Self–Timed Write
• Separate Data Input and Output Pins
• Transparent–Write and Pass–Through
• High Output Drive Capability: 50 pF/Output at Rated Access Time
• Boundary Scan Implementation
• PBGA Package for High Speed Operation
PIN ASSIGNMENT
1 2 3 4 5 6 7 89
A
E W VCC SDI SDO A4 A0
B
A16 A14 G K VSS A6 A2 VSS D8
C
D7 A15 A17 VSS VSS VSS VSS Q8 VSS
D _{VSS Q7 VSS VSS VSS VSS VSS Q6 D6}
E
D5 VSS VSS VSS VSS VSS VSS VSS VCC
F
VCC Q5 VSS VSS VSS VSS VSS D4 Q4
G
D3 Q3 VSS VSS VSS VSS VSS D2 Q2
H
VSS D1 A18 VSS VSS VSS VSS D0 VSS
J
Q1 A12 A10 VSS A9 A8 A5 A1 Q0
K
A13 A11 SCK VCC SE A7 A3
TOP VIEW
86–BUMP
Not to Scale
This document contains information on a new product. Specifications and information herein are subject to change without notice.
REV 3
12/23/97
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MCM67Q909
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