MC33389 Datasheet, PDF (8/35 Pages) Motorola, Inc – System Basis Chip with Low Speed Fault Tolerant CAN

Parameter
MC33389
Freescale Semiconductor, Inc.
Symbol Min
Typ
Max
Unit
Test Conditions
SCLK Clock High Time
t_wSCLKH
175
ns
SCLK Clock Low Time
t_wSCLKL
175
ns
Falling Edge of CSB to Rising
Edge of SCLK
t_lead
250
50
ns
Falling Edge of SCLK to Rising
Edge of CSB
t_lead
250
50
ns
SI to Falling Edge of SCLK
Falling Edge of SCLK to SI
SO Rise Time (CL = 220pF)
SO Fall Time (CL = 220pF)
SI, CSB, SCLK Incoming
Signal Rise Time
t_SISU
125
25
ns
t_SI(hold)
125
25
ns
t_rSO
25
75
ns
t_fSO
25
75
ns
t_rSI
200
ns
SI, CSB, SCLK Incoming
Signal Fall Time
t_fSI
200
Time from Falling Edge of CSB to SO
Low Impedance
High Impedance
t_SO(en)
t_SO(dis)
Time from Rising Edge of
SCLK to SO Data Valid
t_valid
200
200
50
125
SOFTWARE WATCHDOG TIMINGS
(note 1: software watchdog timing accuracy are based on the running mode oscillator tolerance)
ns
0.2 V1 or V2≤SO≥ 0.8V1 or
V2, C_L=200pF
Running mode oscillator tolerance
-12
+12
%
normal request, normal and
standby modes. (Note 1)
Software Watchdog Timing 1
SWt1
4.4
5
5.6
ms
(Note 1)
Software Watchdog Timing 2
SWt2
8.8
10
11.2
ms
(Note 1)
Software Watchdog Timing 3
SWt3
17.6
20
22.4
ms
(Note 1)
Software Watchdog Timing 4
SWt4
28
32
36
ms
(Note 1)
Software Watchdog Timing 5
SWt5
44.8
51
58
ms
(Note 1)
Software Watchdog Timing 6
SWt6
65
74
83
ms
(Note 1)
Software Watchdog Timing 7
SWt7
88
100
112
ms
(Note 1)
Software Watchdog Timing 8
SWt8
178
202
226
ms
(Note 1)
FORCED WAKE-UP AND CYCLIC SENSE TIMINGS
(note 2: cyclic sense and forced wake up timing accuracy are based on the sleep mode oscillator tolerance)
Sleep mode oscillator tolerance
-30
+30
%
sleep mode (Note 2)
Cyclic Sense / FWU timing 1
CYt1
22.4
32
41.6
ms
sleep mode (Note 2)
Cyclic Sense / FWU timing 2
CYt2
44.8
64
83.2
ms
sleep mode (Note 2)
Cyclic Sense / FWU timing 3
CYt3
89.6
128
166.4
ms
sleep mode (Note 2)
MC33389
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