MC88920 Datasheet, PDF (6/10 Pages) Motorola, Inc – LOW SKEW CMOS PLL CLOCK DRIVER With Power-Down/ Power-Up Feature

MC88920
Application Notes
1. Several specifications can only be measured when the
MC88920 is in phase–locked operation. It is not possible
to have the part in phase–lock on ATE (automated test
equipment). Statistical characterization techniques were
used to guarantee those specifications which cannot be
measured on the ATE. MC88920 units were fabricated
with key transistor properties intentionally varied to create
a 14 cell designed experimental matrix. IC performance
was characterized over a range of transistor properties
(represented by the 14 cells) in excess of the expected
process variation of the wafer fabrication area. IC
performance to each specification and fab variation were
used to set performance limits of ATE testable
specifications within those which are to be guaranteed by
statistical characterization. In this way, all units passing
the ATE test will meet or exceed the non–tested
specifications limits.
2. A 1MΩ resistor tied to either Analog VCC or Analog GND,
as shown in Figure 2, is required to ensure no jitter is
present on the MC88920 outputs. This technique causes
a phase offset between the SYNC input and the Q0
output, measured at the pins. The tPD spec describes how
this offset varies with process, temperature, and voltage.
The specs were arrived at by measuring the phase
relationship for the 14 lots described in note 1 while the
part was in phase–locked operation. The actual
measurements were made with a 10MHz SYNC input
(1.0ns edge rate from 0.8V to 2.0V). The phase
measurements were made at 1.5V. See Figure 2 for a
graphical description.
3. Two specs (tRISE/FALL and tPULSE Width 2X_Q output,
see AC Specifications) guarantee that the MC88920
meets the 20MHz and 25MHz 68040 P–Clock input
specification (at 40MHz and 50MHz). For these two specs
to be guaranteed by Motorola, the termination scheme
shown in Figure 3 must be used. For applications which
require 1.5V thresholds, but do not require a tight duty
cycle the RP resistor can be ignored.
4. The tPD spec (SYNC to Q/2) guarantees how close the
Q/2 output will be locked to the reference input connected
to the SYNC input (including temperature and voltage
variation). This also tells what the skew from the Q/2
output on one part connected to a given reference input, to
the Q/2 output on one or more parts connected to that
reference input (assuming equal delay from the
referenceinput to the SYNC input of each part). Therefore
the tPD spec is equivalent to a part–to–part specification.
However, to correctly predict the skew from a given output
on one part to any other output on one or more other parts,
the distribution of each output in relation to the SYNC
input must be known. This distribution for the MC88920 is
provided in Table 1.
TABLE 1. Distribution of Each Output versus SYNC
Output
2X_Q
Q0
Q1
Q2
Q3
Q/2
–(ps)
TBD
TBD
TBD
TBD
TBD
TBD
+(ps)
TBD
TBD
TBD
TBD
TBD
TBD
EXTERNAL
LOOP FILTER
RC1
330Ω R2
0.1µF
C1
1M
REFERENCE
RESISTOR
ANALOG VCC _RC1
1M
REFERENCE
RESISTOR
330Ω R2
0.1µF
C1
ANALOG GND
WITH THE 1MΩ RESISTOR TIED IN THIS FASHION THE TPD
SPECIFICATION, MEASURED AT THE INPUT PINS IS:
tPD = 2.25ns ± 1.0ns (TYPICAL VALUES)
3V
SYNC INPUT
2.25ns
OFFSET
5V
Q0 OUTPUT
ANALOG GND
WITH THE 1MΩ RESISTOR TIED IN THIS FASHION THE TPD
SPECIFICATION, MEASURED AT THE INPUT PINS IS:
tPD = –0.80ns ± 0.30ns
SYNC INPUT
–0.8ns
OFFSET
Q0 OUTPUT
3V
5V
Figure 2. Depiction of the Fixed SYNC to Q0 Offset (tPD) Which Is Present
When a 1MΩ Resistor Is Tied to VCC or Ground
MOTOROLA
6
TIMING SOLUTIONS
BR1333 — REV 5