MC88920 Datasheet, PDF (4/10 Pages) Motorola, Inc – LOW SKEW CMOS PLL CLOCK DRIVER With Power-Down/ Power-Up Feature

MC88920
RST_OUT
RST_IN
SYNC1
LOCK INDICATOR AND
RESET_OUT 1024 CYCLE
COUNT CIRCUITRY
RC1
PFD
CH
PUMP
VCO
PLL_EN
01
POWER–ON
÷2
RESET
MR
D
Q
R
D
Q
R
D
Q
R
D
Q
Q
R
2X_Q
Q0
Q1
Q2
“Dummy” Flip–Flop to Maintain
Phase–Locked Operation
D
Q
Q3
R
D
Q
Q/2
R
Figure 1. MC88920 Logic Block Diagram
SYNC INPUT TIMING REQUIREMENTS
Symbol
tRISE/FALL
SYNC Input
tCYCLE,
SYNC Input
Duty Cycle
Parameter
Rise/Fall Time, SYNC Input
From 0.8V to 2.0V
Input Clock Period
SYNC Input
Duty Cycle, SYNC Input
Minimum
Maximum
Unit
—
5.0
ns
1
200
ns
f2X_Qń4
50% ± 25%
FREQUENCY SPECIFICATIONS (TA = 0°C to 70°C; VCC = 5.0V ± 5%)
Symbol
Fmax (2X_Q)
Fmax (‘Q’)
Parameter
Maximum Operating Frequency, 2X_Q Output
Maximum Operating Frequency,
Q0–Q2, Q3 Outputs
Guaranteed Minimum
50
25
1. Maximum Operating Frequency is guaranteed with the 88920 in a phase–locked condition, and all outputs loaded at 50pF.
Unit
MHz
MHz
MOTOROLA
4
TIMING SOLUTIONS
BR1333 — REV 5