MC34152 Datasheet, PDF (6/10 Pages) ON Semiconductor – HIGH SPEED DUAL MOSFET DRIVERS

MC34152 MC33152
the 5.8 V upper threshold. The lower UVLO threshold is 5.3 V,
yielding about 500 mV of hysteresis.
Power Dissipation
Circuit performance and long term reliability are enhanced
with reduced die temperature. Die temperature increase is
directly related to the power that the integrated circuit must
dissipate and the total thermal resistance from the junction to
ambient. The formula for calculating the junction temperature
with the package in free air is:
TJ = TA + PD (R_θJA)
where: TJ = Junction Temperature
TA = Ambient Temperature
PD = Power Dissipation
R_θJA = Thermal Resistance Junction to Ambient
completely switch the MOSFET ‘on,’ the gate must be
brought to 10 V with respect to the source. The graph shows
that a gate charge Qg of 110 nC is required when operating
the MOSFET with a drain to source voltage VDS of 400 V.
Figure 17. Gate–to–Source Voltage
versus Gate charge
16
MTM15B50
ID = 15 A
TA = 25°C
12
VDS = 100 V
VDS = 400 V
8.0
8.9 nF
There are three basic components that make up total
power to be dissipated when driving a capacitive load with
respect to ground. They are:
PD = PQ + PC _{+ PT}
where:
PQ = Quiescent Power Dissipation
PC = Capacitive Load Power Dissipation
PT = Transition Power Dissipation
The quiescent power supply current depends on the
supply voltage and duty cycle as shown in Figure 16. The
device’s quiescent power dissipation is:
PQ = VCC (ICCL [1–D] + ICCH [D])
where: ICCL = Supply Current with Low State Drive
Outputs
ICCH = Supply Current with High State Drive
Outputs
D = Output Duty Cycle
The capacitive load power dissipation is directly related to
the load capacitance value, frequency, and Drive Output
voltage swing. The capacitive load power dissipation per
driver is:
PC = VCC (VOH – VOL) CL f
where:
VOH = High State Drive Output Voltage
VOL = Low State Drive Output Voltage
CL = Load Capacitance
f = Frequency
4.0
2.0 nF
∆ Qg
CGS = _{∆ VGS}
0
0
40
80
120
160
Qg, GATE CHARGE (nC)
The capacitive load power dissipation is directly related to the
required gate charge, and operating frequency. The
capacitive load power dissipation per driver is:
PC(MOSFET) = VCC Qg f
The flat region from 10 nC to 55 nC is caused by the
drain–to–gate Miller capacitance, occurring while the
MOSFET is in the linear region dissipating substantial
amounts of power. The high output current capability of the
MC34152 is able to quickly deliver the required gate charge
for fast power efficient MOSFET switching. By operating the
MC34152 at a higher VCC, additional charge can be provided
to bring the gate above 10 V. This will reduce the ‘on’
resistance of the MOSFET at the expense of higher driver
dissipation at a given operating frequency.
The transition power dissipation is due to extremely short
simultaneous conduction of internal circuit nodes when the
Drive Outputs change state. The transition power dissipation
per driver is approximately:
PT ≈ VCC (1.08 VCC CL f – 8 x 10–4)
PT must be greater than zero.
When driving a MOSFET, the calculation of capacitive load
power PC is somewhat complicated by the changing gate to
source capacitance CGS as the device switches. To aid in this
calculation, power MOSFET manufacturers provide gate
charge information on their data sheets. Figure 17 shows a
curve of gate voltage versus gate charge for the Motorola
MTM15N50. Note that there are three distinct slopes to the
curve representing different input capacitance values. To
Switching time characterization of the MC34152 is
performed with fixed capacitive loads. Figure 13 shows that
for small capacitance loads, the switching speed is limited by
transistor turn–on/off time and the slew rate of the internal
nodes. For large capacitance loads, the switching speed is
limited by the maximum output current capability of the
integrated circuit.
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MOTOROLA ANALOG IC DEVICE DATA