MC13110A Datasheet, PDF (56/68 Pages) Motorola, Inc – UNIVERSAL CORDLESS TELEPHONE SUBSYSTEM IC

MC13110A/B MC13111A/B
Voltage Reference Adjustment
Switched Capacitor Filter Clock Programming
An internal 1.5 V bandgap voltage reference provides the
A block diagram of the switched capacitor filter clock
voltage reference for the “BD1 Out” and “BD2 Out” low battery
divider is show in Figure 132. There is a fixed divide by 2 after
detect circuits, the “PLL Vref” voltage regulator, the “VB”
the programmable divider. The switched capacitor filter clock
reference, and all internal analog ground references. The
value is given by the following equation;
initial tolerance of the bandgap voltage reference is ±6%. The
tolerance of the internal reference voltage can be improved to
(SCF Clock) = F(2nd LO) / (SCF Divider Value * 2).
±1.5% through MPU serial interface programming. During
The scrambler modulation clock frequency (SMCF) is
final test of the telephone, the battery detect threshold is
proportional to the SCF clock. The following equation defines
measured. Then, the internal reference voltage value is
its value:
adjusted electronically through the MPU serial interface to
achieve the desired accuracy level. The voltage reference
SMCF = (SCF Clock)/40
register value should be stored in ROM during final test so
The SCF divider should be set to a value which brings the
that it can be reloaded each time the MC13110A/B or
SCF Clock as close to 165.16 kHz as possible. This is based
MC13111A/B is powered up (see Figure 131).
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Figure 131. Bandgap Voltage Reference Adjustment
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ^{VrefAdj. VrefAdj. VrefAdj. VrefAdj. VrefAdj. Vref Adj.}
Bit #3 Bit #2 Bit #1 Bit #0
#
Amount
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₀
0
0
0
0
–9.0%
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₀
0
0
1
1
–7.8%
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₀
0
1
0
2
–6.6%
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 0
0
1
1
3
–5.4%
0
1
0
0
4
–4.2%
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₀
1
0
1
5
–3.0%
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₀
1
1
0
6
–1.8%
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₀
1
1
1
7
–0.6%
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₁
0
0
0
8
+0.6 %
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 1
0
0
1
9
+1.8 %
1
0
1
0
10
+3.0 %
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₁
0
1
1
11
+4.2 %
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₁
1
0
0
12
+5.4 %
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₁
1
0
1
13
+6.6 %
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₁
1
1
0
14
+7.8 %
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₁
1
1
1
15
+9.0 %
on the 2nd LO frequency which is chosen in Figure 114.
Figure 132. SCF Clock Divider Circuit
LO2 In
2nd LO
Crystal
LO2 Out
6–b
Programmable
SCF Clock Counter
SCF
Divide ^Clock
By 2.0
MC13110A/B
only
Divide
By 40
Scrambler
Modulation
Clock
Corner Frequency Programming for MC13110A/B and
MC13111A/B
Four different corner frequencies may be selected by
programming the SCF Clock divider as shown in Figures 133
and 134. It is important to note, that all filter corner
frequencies will change proportionately with the SCF Clock
Frequency and Scrambler Modulation Frequency. The
power–up default SCF Clock divider value is 31.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{Figure 133. Corner Frequency Programming for 10.240 MHz 2nd LO}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _MC13111A/B
MC13110A/B
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{SCF Clock}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _Divider
Total
Divide
Value
SCF Clock
Rx Upper
Corner
Tx Upper
Corner
Freq. (kHz) Frequency (kHz) Frequency (kHz)
Scrambler
Modulation
Frequency
(Clk/40) (kHz)
Scrambler
Lower Corner
Frequency (Hz)
Scrambler
Upper Corner
Frequency (kHz)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₂₉
58
176.55
4.147
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 30
60
170.67
4.008
31
62
165.16
3.879
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₃₂
64
160.00
3.758
3.955
3.823
3.700
3.584
4.414
4.267
4.129
4.000
267.2
258.3
250.0
242.2
3.902
3.772
3.650
3.536
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{NOTE: 18. All filter corner frequencies have a tolerance of ±3%.}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ^{19. Rx and Tx Upper Corner Frequencies are the same corner frequencies for the MC13110A/B in scrambler bypass}
56
MOTOROLA ANALOG IC DEVICE DATA