MMDF3N03HD Datasheet, PDF (5/10 Pages) Motorola, Inc – DUAL TMOS POWER MOSFET 4.1 AMPERES 30 VOLTS

MMDF3N03HD
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is for-
ward biased. Curves are based upon maximum peak junc-
tion temperature and a case temperature (TC) of 25°C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance – Gen-
eral Data and Its Use.”
Switching between the off–state and the on–state may tra-
verse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded, and that the transition
time (tr, tf) does not exceed 10 µs. In addition the total power
averaged over a complete switching cycle must not exceed
(TJ(MAX) – TC)/(R_θJC).
A power MOSFET designated E–FET can be safely used
in switching circuits with unclamped inductive loads. For reli-
able operation, the stored energy from circuit inductance dis-
sipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases non–linearly with an
increase of peak current in avalanche and peak junction tem-
perature.
Although many E–FETs can withstand the stress of drain–
to–source avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous cur-
rent (ID), in accordance with industry custom. The energy rat-
ing must be derated for temperature as shown in the
accompanying graph (Figure 9). Maximum energy at cur-
rents below rated continuous ID can safely be assumed to
equal the values indicated.
1200
VDS = 0 V VGS = 0 V
Ciss
1000
TJ = 25°C
800
600 _Crss
Ciss
400
200
Coss
Crss
0
10 5
0
5 10 15 20 25 30
VGS VDS
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 8. Capacitance Variation
1000
VDD = 15 V
ID = 3 A
VGS = 10 V
TJ = 25°C
100
td(off)
tr
10
tf
td(on)
1
1
10
100
RG, GATE RESISTANCE (OHMS)
Figure 10. Resistive Switching Time Variation
versus Gate Resistance
12
24
QT
9
VDS
18
VGS
6
12
Q1
Q2
3
6
Q3
ID = 3 A
TJ = 25°C
0
0
0
2
4
6
8
10
12
Qg, TOTAL GATE CHARGE (nC)
Figure 9. Gate–to–Source and
Drain–to–Source Voltage versus Total Charge
3.0
TJ = 25°C
VGS = 0 V
2.5
2.0
1.5
1.0
0.5
0
0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85
VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
Figure 11. Diode Forward Voltage
versus Current
Motorola TMOS Power MOSFET Transistor Device Data
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