MC88916 Datasheet, PDF (5/9 Pages) Motorola, Inc – LOW SKEW CMOS PLL CLOCK DRIVER WITH PROCESSOR RESET

MC88916
AC CHARACTERISTICS (TA = –40°C to +85°C; VCC = 5.0V ± 5%)
Symbol
Parameter
Mimimum
tRISE/FALL¹
Rise/Fall Time, All Outputs into a 50Ω
0.3
All Outputs
Load
tRISE/FALL¹
Rise/Fall Time into a 20pF Load, With
0.5
2X_Q Output
Termination Specified in AppNote 3
tpulse _width(a)¹
(Q0, Q1, Q2, Q3)
tpulse _width(b)¹
(2X_Q Output)
tPD^1,4
SYNC – Q/2
Output Pulse Width
Q0, Q1, Q2, Q3 at VCC/2
Output Pulse Width
2X_Q at VCC/2
40–49MHz
50–65MHz
66–80MHz
SYNC Input to Q/2 Output Delay
(Measured at SYNC and Q/2 Pins)
0.5tcycle – 0.5
0.5tcycle – 1.5⁵
0.5tcycle – 1.0⁵
0.5tcycle – 0.5
–0.75
+1.25 ⁷
tSKEWr^1,2
Output–to–Output Skew
—
(Rising)
Between Outputs Q0–Q2, Q/2
(Rising Edge Only)
tSKEWf^1,2
Output–to–Output Skew
—
(Falling)
Between Outputs Q0–Q2
(Falling Edge Only)
tSKEWall^1,2
Output–to–Output Skew
—
2X_Q, Q/2, Q0–Q2 Rising
Q3 Falling
tLOCK³
Phase–Lock Acquisition Time,
1
All Outputs to SYNC Input
Maximum
Unit
Condition
1.6
ns tRISE – 0.8V to 2.0V
tFALL – 2.0V to 0.8V
1.6
ns tRISE – 0.8V to 2.0V
tFALL – 2.0V to 0.8V
0.5tcycle + 0.5
ns 50Ω Load Terminated to
VCC/2 (See App Note 3)
0.5tcycle + 1.5⁵ ns 50Ω Load Terminated to
0.5tcycle + 1.0⁵
VCC/2 (See App Note 3)
0.5tcycle + 0.5
–0.15
ns With 1MΩ From RC1
to An VCC
(See Application Note 2)
+3.25 ⁷
ns With 1MΩ From RC1
to An GND
(See Application Note 2)
500
ps Into a 50Ω Load
Terminated to VCC/2
(See Timing Diagram in
Figure 6)
1.0
ns Into a 50Ω Load
Terminated to VCC/2
(See Timing Diagram in
Figure 6)
1.0
ns Into a 50Ω Load
Terminated to VCC/2
(See Timing Diagram in
Figure 6)
10
ms
tPHL MR – Q
Propagation Delay,
MR to Any Output (High–Low)
1.5
13.5
ns Into a 50Ω Load
Terminated to VCC/2
(See Timing Diagram in
Figure 6)
tREC, MR to
Reset Recovery Time rising MR edge
9
SYNC⁶
to falling SYNC edge
tW, MR LOW⁶
Minimum Pulse Width, MR input Low
5
tW, RST_IN LOW Minimum Pulse Width, RST_IN Low
10
tPZL
Output Enable Time
1.5
RST_IN Low to RST_OUT Low
—
ns
—
ns
—
ns When in Phase–Lock
16.5
ns See Application
Note 5
tPLZ
Output Enable Time
RST_IN High to RST_OUT High Z
1016 ‘Q’ Cycles 1024 ‘Q’ Cycles ns
(508 Q/2 Cycles) (512 Q/2 Cycles)
See Application
Note 5
1. These specifications are not tested, they are guaranteed by statistical characterization. See Application Note 1 for a discussion of this
methodology.
2. Under equally loaded conditions and at a fixed temperature and voltage.
3. With VCC fully powered–on: tCLOCK Max is with C1 = 0.1µF; tLOCK Min is with C1 = 0.01µF.
4. See Application Note 4 for the distribution in time of each output referenced to SYNC.
5. Limits do not meet requirements of the 68040 microprocessor. Refer to the 88920 for a low frequency 68040 clock driver.
6. Specification is valid only when the PLL_EN pin is low.
7. This is a typical specification only, worst case guarantees are not provided.
TIMING SOLUTIONS
5
BR1333 — REV 5
MOTOROLA