MC88916 Datasheet, PDF (2/9 Pages) Motorola, Inc – LOW SKEW CMOS PLL CLOCK DRIVER WITH PROCESSOR RESET

MC88916
Q3 1
VCC 2
MR 3
RST_IN 4
VCC(AN) 5
RC1 6
GND(AN) 7
SYNC 8
GND 9
Q0 10
20 GND
19 2X_Q
18 Q/2
17 VCC
16 Q2
15 GND
14 RST_OUT(LOCK)
13 PLL_EN
12 Q1
11 VCC
Pinout: 20–Lead Wide SOIC Package (Top View)
Description of the RST_IN/RST_OUT(LOCK) Functionality (continued)
After the system start–up is complete and the 88916 is
phase–locked to the SYNC input signal (RST_OUT high), the
processor reset functionality can be utilized. When the
RST_IN pin is toggled low (min. pulse width=10nS),
RST_OUT(LOCK) will go to the low state and remain there
for 1024 cycles of the ‘Q’ output frequency (512 SYNC
cycles). During the time in which the RST_OUT(LOCK) is
actively pulled low, all the 88916 clock outputs will continue
operating correctly and in a locked condition to the SYNC
input (clock signals to the 68030/040 family of processors
must continue while the processor is in reset). A propagation
delay after the 1024th cycle RST_OUT(LOCK) goes back to
the high impedance state to be pulled high by the resistor.
Power Supply Ramp Rate Restriction for Correct 68030
Processor Reset Operation During System Start–up
Because the RST_OUT(LOCK) pin is an indicator of
phase–lock to the reference source, some constraints must
be placed on the power supply ramp rate to make sure the
RST_OUT(LOCK) signal holds the processor in reset during
system start–up (power–up). With the recommended loop
filter values (see Figure 7) the lock time is approximately
10ms. The phase–lock loop will begin attempting to lock to a
reference source (if it is present) when VCC reaches 2V. If
the VCC ramp rate is significantly slower than 10ms, then the
PLL could lock to the reference source, causing
RST_OUT(LOCK) to go high before the 88916 and 68030
processor is fully powered up, violating the processor reset
specification. Therefore, if it is necessary for the RST_IN pin
to be held high during power–up, the VCC ramp rate must be
less than 10mS for proper 68030/040 reset operation.
This ramp rate restriction can be ignored if the RST_IN pin
can be held low during system start–up (which holds
RST_OUT low). The RST_OUT(LOCK) pin will then be
pulled back high 1024 cycles after the RST_IN pin goes high.
CAPACITANCE AND POWER SPECIFICATIONS
Symbol
Parameter
CIN
CPD
PD1
Input Capacitance
Power Dissipation Capacitance
Power Dissipation at 33MHz With 50Ω
Thevenin Termination
PD2
Power Dissipation at 33MHz With 50Ω
Parallel Termination to GND
Value Typ
Unit
4.5
pF
40
pF
15mW/Output
mW
90mW/Device
37.5mW/Output
mW
225mW/Device
Test Conditions
VCC = 5.0V
VCC = 5.0V
VCC = 5.0V
T = 25°C
VCC = 5.0V
T = 25°C
MOTOROLA
2
TIMING SOLUTIONS
BR1333 — REV 5