MC44463 Datasheet, PDF (5/8 Pages) Motorola, Inc – REPLAY AND MULTIPLE PICTURE–IN–PICTURE (PIP) CONTROLLER

MC44463
I2C REGISTER DESCRIPTIONS
Base write address = 26h
Base read address = 27h
Read Register
There are two active bits in the single read byte available
from the MC44463 as follows:
Write Vertical Indicator (WVI0) – D7
When 0 indicates that the write operation specified by the
last I2C command has been completed.
PIP Sync Detect Bit (PSD0) – D1
When 0 indicates that the PIP video H pulses are present
and the horizontal timebase oscillator is within acceptable
limits.
Write Registers
Read Start Position/Write Start Position Registers
Sub–address = 00h
Write Raster Position Start Bits (WPS0–2) – D0–D2
Establishes the horizontal beginning of the PIP and its
black level measurement gate. This beginning may be varied
by approximately 3.0 µs. The position of this pulse may be
observed through the Multi Test Pin 30 (See Test Mode
Register Sub–address 03h).
Read Raster Position Bits (RPS0–3) – D4–D7
Establishes the clamp gate position for the black level
reference for the main picture. This position may be varied by
approximately 5.0 µs. The position of this pulse may be
observed through the Multi Test Pin 30 (See Test Mode
Register Sub–address 03h).
Pip Switch Delay/Vertical Filter Register
Sub–address = 01h
PIP Switch Delay Bits (PSD0–3) – D0–D3
Delays the start of PIP on time relative to the PIP picture.
These bits are used to center the PIP border and PIP picture
in the horizontal direction.
Vertical Filter Bit (VFON) – D4
When the filter is activated (VFON = 1) a three line
weighted average is taken to provide the data stored in the
field memory.
Border Color Register
Sub–address = 02h
Border Color Bits (BC0–2) – D0–D2
These Bits control the color of the border. Note that when
using one of the saturated border colors it is possible to get
objectionable dot crawl at the edge of the border in some TVs
unless appropriate comb filtering is used in the TV circuitry.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{BC (2:0)}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₀₀₀
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₀₀₁
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₀₁₀
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₀₁₁
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₁₀₀
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₁₀₁
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₁₁₀
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₁₁₁
Border Color
Black
White 70%
No Border (clear)
No Border (clear)
Blue
Green
Red
White
Test Mode/Main Vertical and Horizontal Polarity Register
Sub–address = 03h
Internal Test Mode Register (ITM0–2) – D0–D2
Sets the Multi Test Pin output to provide one of several
internal signals for test and production alignment. Also
controls the test memory address counter.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{ITM (2:0)}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₀₀₀
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₀₀₁
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₀₁₀
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₀₁₁
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₁₀₀
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₁₀₁
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₁₁₀
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₁₁₁
Multi–Test I/O and Function
Input – Analog Test mode
Input – Digital Test mode
Output – Sync Detect
Output – PIP Switch
Output – PIP H Detect
Output – PIP V Detect
Output – PIP Clamp
Output – Main Clamp
Main vertical polarity select bit (MVP0) – D6
Selects polarity of active level of vertical reference input.
0 = positive going, 1 = negative going.
Main horizontal polarity select bit (MHP0) – D7
Selects polarity of active level of horizontal reference
input. 0 = positive going, 1 = negative going.
PIP Freeze/PIP Size/Main and PIP Video Source Register
Sub–address = 04h
LIVE PIP Select Bits (LIVE_P0–1) – D0–D1
Selects which of the mutliple PIP pictures is the active
“live” one.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{LIVE_P (1:0)}
1/16 Size
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₀₀
Top = LIVE
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₀₁
2nd from Top = LIVE
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₁₀
3rd from Top = LIVE
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₁₁
4th from Top = LIVE
1/9 Size
Top = LIVE
2nd from Top = LIVE
3rd from Top = LIVE
3rd from Top = LIVE
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{PIP Freeze Bit (STIL0) – D4}
When set to one, the most recently received field is
continuously displayed until the freeze bit is cleared.
PIP Size Bit (PSI90) – D5
Switches the PIP size between 1/16 main size (when 0)
and 1/9 main size (when 1).
Main Video Source Select Bit (MSEL0) – D6
Selects which video input will be applied to the PIP switch
as the main video out.
PIP Video Source Select Bit (PSEL0) – D7
Selects which video input will be applied to the video
decoder to provide the PIP video.
MSEL/PSEL
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₀
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ¹
Function
Video 1 Input to Main/
Video 1 Input to PIP
Video 2 Input to Main/
Video 2 Input to PIP
MOTOROLA ANALOG IC DEVICE DATA
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