MC56F8323 Datasheet, PDF (49/140 Pages) Motorola, Inc – 16-bit Hybrid Controllers

Peripheral Memory Mapped Registers
Table 4-24 System Integration Module Registers Address Map
(SIM_BASE = $00 F350)
Register Acronym Address Offset
Register Description
SIM_CONTROL
$0
SIM_RSTSTS
$1
SIM_SCR0
$2
SIM_SCR1
$3
SIM_SCR2
$4
SIM_SCR3
$5
SIM_MSH_ID
$6
SIM_LSH_ID
$7
SIM_PUDR
$8
SIM_CLKOSR
$A
SIM_GPS
$B
SIM_PCE
$C
SIM_ISALH
$D
SIM_ISALL
$E
Control Register
Reset Status Register
Software Control Register 0
Software Control Register 1
Software Control Register 2
Software Control Register 3
Most Significant Half JTAG ID
Least Significant Half JTAG ID
Pull-up Disable Register
Reserved
Clock Out Select Register
GPIO Peripheral Select Register
Peripheral Clock Enable Register
I/O Short Address Location High Register
I/O Short Address Location Low Register
Table 4-25 Power Supervisor Registers Address Map
(LVI_BASE = $00 F360)
Register Acronym Address Offset
Register Description
LVI_CONTROL
$0
LVI_STATUS
$1
Control Register
Status Register
56F8323 Technical Data, Rev. 11.0
Freescale Semiconductor
49
Preliminary