MC56F8323 Datasheet, PDF (31/140 Pages) Motorola, Inc – 16-bit Hybrid Controllers

Registers
3.5 Registers
When referring to the register definitions for the OCCS in the 56F8300 Peripheral User Manual, use the
register definitions with the internal Relaxation Oscillator, since the 56F8323 and 56F8123 contain this
oscillator.
Part 4 Memory Map
4.1 Introduction
The 56F8323 and 56F8123 devices are 16-bit motor-control chips based on the 56800E core. These parts
use a Harvard-style architecture with two independent memory spaces for Data and Program. On-chip
RAM and Flash memories are used in both spaces.
This section provides memory maps for:
• Program Address Space, including the Interrupt Vector Table
• Data Address Space, including the EOnCE Memory and Peripheral Memory Maps
On-chip memory sizes for the device are summarized in Table 4-1. Flash memories’ restrictions are
identified in the “Use Restrictions” column of Table 4-1.
Note: Data Flash and Program RAM are NOT available on the 56F8123 device.
On-Chip Memory
Table 4-1 Chip Memory Configurations
56F8323
56F8123
Use Restrictions
Program Flash
Data Flash
Program RAM
Data RAM
Program Boot Flash
32KB
8KB
4KB
8KB
8KB
32KB
—
—
8KB
8KB
Erase / Program via Flash interface unit and word
writes to CDBW
Erase / Program via Flash interface unit and word
writes to CDBW. Data Flash can be read via either
CDBR or XDB2, but not by both simultaneously
None
None
Erase / Program via Flash Interface unit and word
writes to CDBW
4.2 Program Map
The Program Memory map is located in Table 4-2. The operating mode control bits (MA and MB) in the
Operating Mode Register (OMR) control the Program Memory map. Because the 56F8323 and 56F8123
do not include EMI, the OMR MA bit, which is used to decide internal or external BOOT, will have no
effect on the Program Memory Map. OMR MB reflects the security status of the Program Flash. After
reset, changing the OMR MB bit will have no effect on the Program Flash.
56F8323 Technical Data, Rev. 11.0
Freescale Semiconductor
31
Preliminary