MMDF2N02E Datasheet, PDF (4/10 Pages) Motorola, Inc – DUAL TMOS MOSFET 3.6 AMPERES 25 VOLTS

MMDF2N02E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are deter-
mined by how fast the FET input capacitance can be charged
by current from the generator.
The published capacitance data is difficult to use for calculat-
ing rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a resis-
tive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG – VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
1200
VDS = 0 V
1000 _Ciss
VGS = 0 V
TJ = 25°C
800
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate val-
ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG – VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off–state condition when cal-
culating td(on) and is read at a voltage corresponding to the
on–state when calculating td(off).
At high switching speeds, parasitic circuit elements com-
plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func-
tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea-
sure and, consequently, is not specified.
12
16
QT
9
VDS
VGS
12
600 ^Crss
400
Ciss
Coss
200
Crss
0
10
5
0
5
10
15
20
25
VGS VDS
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
100
VDD = 10 V
ID = 2 A
VGS = 10 V
TJ = 25°C
td(off)
tf
tr
10
td(on)
6
8
Q1
Q2
3
4
Q3
0
0
2
4
6
8
Qg, TOTAL GATE CHARGE (nC)
ID = 2.3 A
TJ = 25°C
0
10
12
Figure 8. Gate–to–Source and
Drain–to–Source Voltage versus Total Charge
7
TJ = 25°C
6 ^{VGS = 0 V}
5
4
3
2
1
1
10
100
RG, GATE RESISTANCE (OHMS)
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
1
0
0.5
0.6
0.7
0.8
0.9
1
1.1
VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage
versus Current
4
Motorola TMOS Power MOSFET Transistor Device Data