MC74VHC139 Datasheet, PDF (4/6 Pages) Motorola, Inc – Dual 2-to-4 Decoder/Demultiplexer

MC74VHC139
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{DC ELECTRICAL CHARACTERISTICS}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _Symbol
Parameter
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _Iin
Maximum Input
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Leakage Current
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ICC MaximumQuiescent
Supply Current
Test Conditions
Vin = 5.5 V or GND
Vin = VCC or GND
VCC
V
0 to 5.5
TA = 25°C
Min
Typ
Max
± 0.1
5.5
4.0
TA = – 40 to 85°C
Min
Max Unit
± 1.0
µA
40.0
µA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _Symbol
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _tPLH,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPHL
Parameter
Maximum Propagation Delay,
A to Y
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _tPLH,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _tPHL
Maximum Propagation Delay,
E to Y
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _Cin
Maximum Input Capacitance
Test Conditions
VCC = 3.3 ± 0.3V
VCC = 5.0 ± 0.5V
VCC = 3.3 ± 0.3V
VCC = 5.0 ± 0.5V
CL = 15pF
CL = 50pF
CL = 15pF
CL = 50pF
CL = 15pF
CL = 50pF
CL = 15pF
CL = 50pF
TA = 25°C
Min
Typ
Max
7.2
11.0
9.7
14.5
5.0
7.2
6.5
9.2
6.4
9.2
8.9
12.7
4.4
6.3
5.9
8.3
4
10
TA = – 40 to 85°C
Min
Max Unit
1.0
13.0 ns
1.0
16.5
1.0
8.5
1.0
10.5
1.0
11.0
ns
1.0
14.5
1.0
7.5
1.0
9.5
10
pF
Typical @ 25°C, VCC = 5.0V
CPD Power Dissipation Capacitance (Note NO TAG)
26
pF
1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR₎ = CPD  VCC  fin + ICC/2 (per decoder). CPD is used to determine the
no–load dynamic power consumption; PD = CPD  VCC2  fin + ICC  VCC.
SWITCHING WAVEFORMS
A
tPLH
Y
50%
50% VCC
VCC
GND
tPHL
Figure 2.
E _50%
Y
tPHL
50% VCC
VCC
GND
tPLH
Figure 3.
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
CL*
* Includes all probe and jig capacitance
Figure 4. Test Circuit
MOTOROLA
4
VHC Data – Advanced CMOS Logic
DL203 — Rev 0