MC74VHC139 Datasheet, PDF (1/6 Pages) Motorola, Inc – Dual 2-to-4 Decoder/Demultiplexer

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Dual 2-to-4 Decoder/
Demultiplexer
The MC74VHC139 is an advanced high speed CMOS 2–to–4 decoder/
demultiplexer fabricated with silicon gate CMOS technology. It achieves high
speed operation similar to equivalent Bipolar Schottky TTL while maintaining
CMOS low power dissipation.
When the device is enabled (E = low), it can be used for gating or as a data
input for demultiplexing operations. When the enable input is held high, all
four outputs are fixed high, independent of other inputs.
The internal circuit is composed of three stages, including a buffer output
which provides high noise immunity and stable output. The inputs tolerate
voltages up to 7V, allowing the interface of 5V systems to 3V systems.
• High Speed: tPD = 5.0ns (Typ) at VCC = 5V
• Low Power Dissipation: ICC = 4µΑ (Max) at TA = 25°C
• High Noise Immunity: VNIH = VNIL = 28% VCC
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2V to 5.5V Operating Range
• Low Noise: VOLP = 0.8 V (Max)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300mA
• ESD Performance: HBM > 2000V; Machine Model > 200V
• Chip Complexity: 100 FETs or 25 Equivalent Gates
LOGIC DIAGRAM
ADDRESS
INPUTS
A0a ²
A1a ³
Ea ¹
ADDRESS
INPUTS
A0b ¹⁴
A1b ¹³
Eb ¹⁵
4 _Y0a
5 _Y1a
6 _Y2a
7 _Y3a
ACTIVE–LOW
OUTPUTS
12 _Y0b
11 _Y1b
10 _Y2b
9 _Y3b
ACTIVE–LOW
OUTPUTS
MC74VHC139
D SUFFIX
16–LEAD SOIC PACKAGE
CASE 751B–05
DT SUFFIX
16–LEAD TSSOP PACKAGE
CASE 948F–01
M SUFFIX
16–LEAD SOIC EIAJ PACKAGE
CASE 966–01
ORDERING INFORMATION
MC74VHCXXXD
MC74VHCXXXDT
MC74VHCXXXM
SOIC
TSSOP
SOIC EIAJ
PIN ASSIGNMENT
Ea 1
A0a 2
A1a 3
Y0a 4
Y1a 5
Y2a 6
Y3a 7
GND 8
16 VCC
15 Eb
14 _A0b
13 A1b
12 Y0b
11 Y1b
10 Y2b
9 Y3b
FUNCTION TABLE
Inputs
E A1 A0
H
XX
L
LL
L
LH
L
HL
L
HH
Outputs
Y0 Y1 Y2 Y3
H HH H
L HH H
H LH H
H HL H
H HH L
6/97
© Motorola, Inc. 1997
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