MC74HC4049D Datasheet, PDF (4/6 Pages) Motorola, Inc – Hex Buffers/Logic-Level Down Converters

MC54/74HC4049 MC54/74HC4050
LOGIC DETAIL
HC4049
(1/6 of the Device)
A
Y
HC4050
(1/6 of the Device)
A
Y
TYPICAL APPLICATIONS
LSTTL to Low–Voltalge HSCMOS
5V
3V
High–Voltage CMOS to HSCMOS
VDD*
VCC*
IN
OUT
IN
OUT
LSTTL
DEVICE
HC4049
HC4050
HC DEVICE
NOTE: To determine the noise immunity for the LSTTL to low–voltage
configuration, use Eq. 1 and Eq. 2:
(TTL) VOH – (CMOS) VIH
(TTL) VOL – (CMOS) VIL
Eq. 1
Eq. 2
For the supply levels shown:
2.4 – 3 (75%) = 2.4 – 2.25 = 0.15 V
0.4 – 3 (15%) = 0.4 – 0.45 = 0.05 V
Therefore, worst case noise immunity is 50 mV.
For supply levels greater than 4.5 volts use
the 74HCT04A for direct interface to TTL outputs.
STANDARD HC4049
HC DEVICE
ÎÎÎÎÎÎÎ^CM_*T^OÎÎÎÎÎÎÎ_a^S_bV111le522ÎÎÎÎÎÎÎ_DD1VVV. ÎÎÎÎÎÎÎ_S^H_u^C_p⁴ÎÎÎÎÎÎÎ_p⁰⁵_l⁰_yÎÎÎÎÎÎÎ_EVx253aCÎÎÎÎÎÎÎ_{VVVmC p}ÎÎÎÎÎÎÎ_les ÎÎÎÎÎÎÎ
MOTOROLA
4
High–Speed CMOS Logic Data
DL129 — Rev 6