MC68349 Datasheet, PDF (4/7 Pages) Motorola, Inc – HIGH PERFORMANCE INTEGRATED PROCESSOR

Freescale Semiconductor, Inc.
CPU030 CENTRAL PROCESSING UNIT
Processing power for the MC68349 is provided by the CPU030 central processing unit. The CPU030
delivers MC68030 performance in a form factor that is highly optimized for the needs of portable intelligent
personal electronics applications. The CPU030 is a modular processor whose configuration can be modified
to suit the requirements of many different classes of applications.
The CPU030 employed in the MC68349 is composed of three principle modular elements: the CPU32+ 32-
bit processor , a configurable instruction cache module, and a quad data memory module. Memory
management is an option not supported in the MC68349.
CPU32+ PROCESSOR
The CPU32+ processor is the full 32-bit extension of the CPU32 processor found on many M68300 family
of integrated processors and provides the execution units for the CPU030. The CPU32+ provides 32-bit
execution units and 32-bit data paths (internal and external) and has a basic instruction execution rate of
two clock periods for a 32-bit operation. The CPU32+ is completely upward software compatible with the
MC68000 and CPU32.
In addition to performing basic instruction execution, the CPU32+ also provides central power management
capabilities to the MC68349 as well as a sophisticated background debug port for non-invasive
instrumentation in the software development and debug environments.
CONFIGURABLE INSTRUCTION CACHE (CIC)
The CIC is a highly configurable memory resource designed to optimize the supply of instructions to the
CPU030 while moderating power consumption by reducing external accesses. Considerable flexibility in the
handling of instructions is provided by the CIC to allow the operating systems programmer to ensure
deterministic response to real-time events while also maximizing average or statistical performance.
The CIC is composed of four identical blocks each of which can be independently configured as a 256-byte
instruction cache or as a 512-byte static random access memory (SRAM). When configured as an SRAM, a
block is independently relocatable in the system's address space. When configured as a cache, a block
operates as a direct-mapped cache of sixty-four 32-bit entries. When multiple blocks are configured as
caches, set-associativity is supported up to a maximum of four sets. Each cache block can be independently
locked to freeze its internal contents.
Using CIC flexibility, it is feasible to place high-priority interrupt or operating system routines in protected
SRAM, which is always instantly available, while allowing remaining blocks to operate as caches to increase
the performance of general system and user tasks. The CIC configuration can be established at system
initialization or on a task-by-task basis, yielding maximum flexibility.
QUAD DATA MEMORY MODULE (QDMM)
The QDMM provides dedicated data storage resources for the CPU030 in the form of four, independent, 1-
Kbyte SRAM blocks. Each of these blocks can be independently relocated anywhere in the system address
space, and each is independently protected (supervisor/user, read/write).
The QDMM can be used as scratchpad memory, stack caches for independent tasks, buffers for I/O
operations, or parameter storage. The QDMM does not provide direct data caching due to the real-time
nature of its anticipated applications, but provides significant performance and power-management benefits
to MC68349-based systems.
MOTOROLA
MC68349 PRODUCT INFORMATION
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