MC54-74HC157A Datasheet, PDF (4/7 Pages) Motorola, Inc – High–Performance Silicon–Gate CMOS

MC54/74HC157A
PIN DESCRIPTIONS
INPUTS
A0, A1, A2, A3 (Pins 2, 5, 11, 14)
Nibble A inputs. The data present on these pins is trans-
ferred to the outputs when the Select input is at a low level
and the Output Enable input is at a low level. The data is
presented to the outputs in noninverted form.
B0, B1, B2, B3 (Pins 3, 6, 10, 13)
Nibble B inputs. The data present on these pins is trans-
ferred to the outputs when the Select input is at a high level
and the Output Enable input is at a low level. The data is
presented to the outputs in noninverted form.
OUTPUTS
Y0, Y1, Y2, Y3 (Pins 4, 7, 9, 12)
Data outputs. The selected input Nibble is presented at
these outputs when the Output Enable input is at a low level.
The data present on these pins is in its noninverted form. For
the Output Enable input at a high level, the outputs are at a
low level.
CONTROL INPUTS
Select (Pin 1)
Nibble select. This input determines the data word to be
transferred to the outputs. A low level on this input selects
the A inputs and a high level selects the B inputs.
Output Enable (Pin 15)
Output Enable input. A low level on this input allows the
selected input data to be presented at the outputs. A high
level on this input sets all outputs to a low level.
SWITCHING WAVEFORMS
tr
INPUT A OR B
tPLH
OUTPUT Y
90%
50%
10%
90%
50%
10%
tTLH
tf
VCC
GND
tPHL
tTHL
tr
SELECT
tPLH
90%
50%
10%
OUTPUT Y
90%
50%
10%
tTLH
tf
VCC
GND
tPHL
tTHL
Figure 1. HC157A
Figure 2. Y versus Select, Noninverted
tr
OUTPUT
ENABLE
tPHL
OUTPUT Y
90%
50%
10%
90%
50%
10%
tTHL
tf
VCC
GND
tPLH
tTLH
Figure 3. HC157A
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
CL*
* Includes all probe and jig capacitance
Figure 4. Test Circuit
MOTOROLA
4
High–Speed CMOS Logic Data
DL129 — Rev 6