DSP56156 Datasheet, PDF (39/76 Pages) Motorola, Inc – 16-bit Digital Signal Processor

Freescale Semiconductor, Inc.
AC Electrical Characteristics and Timing
Host Port Timing
Host Port Timing
(V_CC = 5.0 V dc ± 10%, T_J = -40° to +125°C, C_L = 50 pF + 1 TTL Load)
T
cyc
t_HSDL
t_suh
= I_CYC / 4
= Clock cycle = ¹/₂ instruction cycle= 2 T cycle
= Host Synchronization Delay Time (See Note 1)
= Host Processor Data Setup Time
Active low lines should be “pulled up” in a manner consistent with the AC and DC specifica-
tions.
Table 19 Host Port Timing
Num
Characteristic
40 MHz
Min
Max
50 MHz
Min
Max
60 MHz
Unit
Min
Max
100 tHSDL Host Synchronous Delay
(See Note 1)
T
3T
T
3T
T
3T
ns
101 HEN/HACK Assertion Width
• CVR, ICR, ISR Read 2T+36
2T+33
2T+30
ns
• Read
32+t_suh
—
29+t_suh
—
26+t_suh
—
• Write
32
—
29
—
26
—
(See Notes 2, 4)
102 HEN/HACK Deassertion Width
(See Note 2)
31
—
29
—
27
—
ns
103 Minimum Cycle Time Between Two 4T+36
—
4T+33
—
4T+30
—
ns
HEN Assertion for Consecutive
CVR, ICR, ISR Reads
104 Host Data Input Setup Time before
5
—
4
—
3
—
ns
HEN/HACK Deassertion
105 Host Data Input Hold Time after
HEN/HACK Deassertion
7
—
6
—
5
—
ns
106 HEN/HACK Assertion to Output
0
—
0
—
0
—
ns
Data Active from High Impedance
107 HEN/HACK Assertion to Output
Data Valid
—
32
—
29
—
26
ns
108 HEN/HACK Deassertion to Output
—
20
—
18.5
—
17
ns
Data High Impedance
109 Output Data Hold Time after
HEN/HACK Deassertion
5
—
5
—
4
—
ns
MOTOROLA
DSP56156 Data Sheet
39
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