DSP56156 Datasheet, PDF (1/76 Pages) Motorola, Inc – 16-bit Digital Signal Processor

Freescale Semiconductor, Inc.
MOTOROLA
SEMICONDUCTOR
Order this document
by DSP56156/D
REV 1
TECHNICAL DATA
DSP56156
Advance Information
DSP56156ROM
16-bit Digital Signal Processor
The DSP56156 is a general-purpose MPU-style Digital Signal Processor (DSP). On a single semi-
conductor chip, the DSP56156 comprises a very efficient 16-bit digital signal processing core, pro-
gram and data memories, a number of peripherals, and system support circuitry. Unique features
of the DSP56156 include a built-in sigma-delta (²ý) codec and phase-locked loop (PLL). This com-
bination of features makes the DSP56156 a cost-effective, high-performance solution for many DSP
applications, especially speech coding, digital communications, and cellular base stations.
The central processing unit of the DSP56156 is the DSP56100 core processor. Like all DSP56100-
based DSPs, the DSP56156 consists of three execution units operating in parallel, allowing up to
six operations to be performed during each instruction cycle. This parallelism greatly increases the
effective processing speed of the DSP56156. The MPU-style programming model and instruction
set allow straightforward generation of efficient, compact code. The basic architectures and devel-
opment tools of Motorola's 16-bit, 24-bit, and 32-bit DSPs are so similar that understanding how to
design and program one greatly reduces the time needed to learn the others.
On-Chip Emulation (OnCE^TM port) circuitry provides convenient and inexpensive debug facil-
ities normally available only through expensive external hardware. Development costs are re-
duced and in-field testing is greatly simplified using the OnCE^TM port. Figure 1 illustrates the
DSP56156 in detail.
7
2
5
5
15
16-bit Bus
Sigma-
Delta
Codec
16-bit
Timer/
Event
Counter
Sync.
Serial
(SSI)
or I/O
Sync.
Serial
(SSI)
or I/O
Host
Interface
(HI)
or I/O
Program
Memory *
2048 × 16 RAM
64 × 16 ROM
(boot)
Data
Memory
2048 × 16 RAM
16-bit
56100 DSP
Core
Internal
Data
Bus
Switch
Address
Generation
Unit
PAB
XAB1
XAB2
GDB
PDB
XDB
External
Address
Bus
Switch
Address
16
External
Data
Bus
Switch
Data
16
OnCE™ Port
PLL
Clock
Gen.
Interrupt
Control
Program
Decode
Controller
Program
Address
Generator
Program Control Unit
Data ALU
16 x 16 + 40 —> 40-bit MAC
Two 40-bit Accumulators
Bus
Control
Control
9
3
4 IRQ 2
* 12 k x 16 ROM replaces the program RAM on the DSP56156ROM
Figure 1 DSP56156 Block Diagram
Specifications and information herein are subject to change without notice.
OnCE is a trademark of Motorola, Inc.
© MOTOROLA INC., 1994
For More Information On This Product,
Go to: www.freescale.com