DSP56002 Datasheet, PDF (33/110 Pages) Motorola, Inc – 24-BIT DIGITAL SIGNAL PROCESSOR

Specifications
External Clock (EXTAL Pin)
EXTAL
ET_H
ET_L
1
2
3
ET_C
4
NOTE: The midpoint is V_ILC + 0.5 (V_IHC – V_ILC).
Figure 2-3 External Clock Timing
Midpoint
V_ILC
V_IHC
AA0360
Table 2-5 Clock Operation
Num
Characteristics
40 MHz
Symbol
Min Max
66 MHz
80 MHz
Min Max Min Max
Unit
Frequency of Operation
(EXTAL Pin)
E_f
0
40
0
66
0
80 MHz
1 Clock Input High
• With PLL disabled
(46.7% – 53.3% duty cycle)
• With PLL enabled
(42.5% – 57.5% duty cycle)
ET_H
11.7 ∞ 7.09 ∞
5.8
∞
ns
10.5 235.5 µs 6.36 235.5 µs 5.3 235.5 µs
2 Clock Input Low
• With PLL disabled
(46.7% – 53.3% duty cycle)
• With PLL enabled
(42.5% – 57.5% duty cycle)
11.7 ∞ 7.09 ∞
5.8
∞
ET_L
ns
10.5 235.5 µs 6.36 235.5 µs 5.3 235.5 µs
3 Clock Cycle Time
• With PLL disabled
• With PLL enabled
ET_C 25
∞ 15.15 ∞ 12.5 ∞
ns
25 409.6 µs 15.15 409.6 µs 12.5 409.6 µs
4 Instruction Cycle Time =
I_CYC = 2T_C
• With PLL disabled
• With PLL enabled
I_CYC
50
∞ 30.3 ∞
25
∞
ns
50 819.2 µs 30.3 819.2 µs 25 819.2 µs
Note: External Clock Input High and External Clock Input Low are measured at 50% of the input
transition.
MOTOROLA
DSP56002/D, Rev. 3
2-7