DSP56002 Datasheet, PDF (1/110 Pages) Motorola, Inc – 24-BIT DIGITAL SIGNAL PROCESSOR

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
24-BIT DIGITAL SIGNAL PROCESSOR
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DSP56002/D, Rev. 3
DSP56002
The DSP56002 is a MPU-style general purpose Digital Signal Processor (DSP) composed of an
efficient 24-bit DSP core, program and data memories, various peripherals, and support
circuitry. The DSP56000 core is fed by on-chip Program RAM, and two independent data RAMs.
The DSP56002 contains a Serial Communication Interface (SCI), Synchronous Serial Interface (SSI),
parallel Host Interface (HI), Timer/Event Counter, Phase Lock Loop (PLL), and an On-Chip
Emulation (OnCE™) port. This combination of features, illustrated in Figure 1, makes the
DSP56002 a cost-effective, high-performance solution for high-precision general purpose digital
signal processing.
1
6
3
15
16-bit Bus
24-bit Bus
24-bit
Timer/
Event
Counter
Sync.
Serial
(SSI)
or I/O
Serial
Comm.
(SCI)
or I/O
Host
Interface
(HI)
or I/O
Program
Memory
512 × 24 RAM
64 × 24 ROM
(boot)
X Data
Memory
256 × 24 RAM
256 × 24 ROM
(A-law/ µ-law)
Y Data
Memory
256 × 24 RAM
256 × 24 ROM
(sine)
24-bit
Address
PAB
56000 DSP
Generation
XAB
Core
Unit
YAB
Internal
Data
Bus
Switch
GDB
PDB
XDB
YDB
OnCE™
Port
Clock
PLL _Gen.
7
Interrupt
Control
Program
Decode
Controller
Program
Address
Generator
Program Control Unit
Data ALU
24 × 24 + 56 → 56-bit MAC
Two 56-bit Accumulators
4
3
IRQ
Figure 1 DSP56002 Block Diagram
External
Address
Bus
Switch
Address
16
External
Data
Bus
Switch
Data
24
Bus
Control
Control
10
AA0604
©1996 MOTOROLA, INC.