68HC912DG128 Datasheet, PDF (316/424 Pages) Motorola, Inc – Advance Information

MSCAN Controller
msCAN12 Bus Timing Register 0 (CBTR0)
CBTR0 R
$0102 W
RESET
Bit 7
SJW1
0
6
SJW0
0
5
BRP5
0
4
BRP4
0
3
BRP3
0
2
BRP2
0
1
BRP1
0
Bit 0
BRP0
0
SJW1, SJW0 — Synchronization Jump Width
The synchronization jump width defines the maximum number of time
quanta (Tq) clock cycles by which a bit may be shortened, or
lengthened, to achieve resynchronization on data transitions on the
bus (see Table 45).
SJW1
0
0
1
1
Table 45 Synchronization jump width
SJW0
0
1
0
1
Synchronization jump width
1 Tq clock cycle
2 Tq clock cycles
3 Tq clock cycles
4 Tq clock cycles
BRP5 – BRP0 — Baud Rate Prescaler
These bits determine the time quanta (Tq) clock, which is used to
build up the individual bit timing, according to Table 46.
BRP5
0
0
0
0
:
:
1
BRP4
0
0
0
0
:
:
1
Table 46 Baud rate prescaler
BRP3
0
0
0
0
:
:
1
BRP2
0
0
0
0
:
:
1
BRP1
0
0
1
1
:
:
1
BRP0
0
1
0
1
:
:
1
Prescaler value (P)
1
2
3
4
:
:
64
NOTE: The CBTR0 register can only be written if the SFTRES bit in CMCR0 is
set.
68HC(9)12DG128 Rev 1.0
316
MSCAN Controller
30-mscan12
MOTOROLA