68HC912DG128 Datasheet, PDF (313/424 Pages) Motorola, Inc – Advance Information

MSCAN Controller
Programmer’s Model of Control Registers
• In cases of more than one buffer having the same lowest priority,
the message buffer with the lower index number wins.
NOTE:
To ensure data integrity, no registers of the transmit buffers shall be
written while the associated TXE flag is cleared.
To ensure data integrity, no registers of the receive buffer shall be read
while the RXF flag is cleared.
ProgrammerÕs Model of Control Registers
Overview
The programmer’s model has been laid out for maximum simplicity and
efficiency.
msCAN12 Module Control Register 0 (CMCR0)
CMCR0 R
$0100 W
RESET
Bit 7
0
0
6
5
4
0
SYNCH
CSWAI
0
1
0
3
TLNKEN
0
2
SLPAK
0
1
SLPRQ
0
Bit 0
SFTRES
1
CSWAI — CAN Stops in Wait Mode
0 = The module is not affected during WAIT mode.
1 = The module ceases to be clocked during WAIT mode.
SYNCH — Synchronized Status
This bit indicates whether the msCAN12 is synchronized to the CAN
bus and as such can participate in the communication process.
0 = msCAN12 is not synchronized to the CAN bus
1 = msCAN12 is synchronized to the CAN bus
TLNKEN — Timer Enable
This flag is used to establish a link between the msCAN12 and the
on-chip timer (see Timer Link).
0 = The port is connected to the timer input.
1 = The msCAN12 timer signal output is connected to the timer
input.
27-mscan12
MOTOROLA
MSCAN Controller
68HC(9)12DG128 Rev 1.0
313