MC68HC912D60A Datasheet, PDF (314/460 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
MSCAN Controller
17.6 Interrupts
The msCAN12 supports four interrupt vectors mapped onto eleven
different interrupt sources, any of which can be individually masked (for
details see msCAN12 Receiver Flag Register (CRFLG) to msCAN12
Transmitter Control Register (CTCR)):
• Transmit interrupt: At least one of the three transmit buffers is
empty (not scheduled) and can be loaded to schedule a message
for transmission. The TXE flags of the empty message buffers are
set.
• Receive interrupt: A message has been successfully received and
loaded into the foreground receive buffer. This interrupt is
generated immediately after receiving the EOF symbol. The RXF
flag is set.
• Wake-up interrupt: An activity on the CAN bus occurred during
msCAN12 internal SLEEP mode.
• Error interrupt: An overrun, error or warning condition occurred.
The receiver flag register (CRFLG) indicates one of the following
conditions:
– Overrun: an overrun condition as described in Receive
Structures has occurred.
– Receiver warning: the receive error counter has reached the
CPU warning limit of 96.
– Transmitter warning: the transmit error counter has reached
the CPU warning limit of 96.
– Receiver error passive: the receive error counter has
exceeded the error passive limit of 127 and msCAN12 has
gone to error passive state.
– Transmitter error passive: the transmit error counter has
exceeded the error passive limit of 127 and msCAN12 has
gone to error passive state.
– Bus off: the transmit error counter has exceeded 255 and
msCAN12 has gone to BUSOFF state.
Technical Data
314
MC68HC912D60A — Rev 3.0
MSCAN Controller
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