MC68HC912D60A Datasheet, PDF (122/460 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Resets and Interrupts
Table 9-1. Interrupt Vector Map
Vector Address
Interrupt Source
$FFFE, $FFFF
$FFFC, $FFFD
$FFFA, $FFFB
$FFF8, $FFF9
$FFF6, $FFF7
$FFF4, $FFF5
$FFF2, $FFF3
$FFF0, $FFF1
$FFEE, $FFEF
$FFEC, $FFED
$FFEA, $FFEB
$FFE8, $FFE9
$FFE6, $FFE7
$FFE4, $FFE5
$FFE2, $FFE3
$FFE0, $FFE1
$FFDE, $FFDF
$FFDC, $FFDD
$FFDA, $FFDB
$FFD8, $FFD9
Reset
Clock monitor fail reset
COP failure reset
Unimplemented instruction trap
SWI
XIRQ
IRQ
Real time interrupt
Timer channel 0
Timer channel 1
Timer channel 2
Timer channel 3
Timer channel 4
Timer channel 5
Timer channel 6
Timer channel 7
Timer overflow
Pulse accumulator overflow
Pulse accumulator input edge
SPI serial transfer complete
$FFD6, $FFD7 SCI 0
$FFD4, $FFD5 SCI 1
$FFD2, $FFD3 ATD0 or ATD1
$FFD0, $FFD1 MSCAN wake-up
$FFCE, $FFCF Key wake-up G or H
$FFCC, $FFCD Modulus down counter underflow
$FFCA, $FFCB Pulse Accumulator B Overflow
$FFC8, $FFC9 MSCAN errors
$FFC6, $FFC7
$FFC4, $FFC5
$FFC2, $FFC3
$FF80–$FFC1
MSCAN receive
MSCAN transmit
CGM lock and limp home
Reserved
CCR
Mask
None
None
None
None
None
X bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
Local Enable
None
COPCTL (CME, FCME)
COP rate selected
None
None
None
INTCR (IRQEN)
RTICTL (RTIE)
TMSK1 (C0I)
TMSK1 (C1I)
TMSK1 (C2I)
TMSK1 (C3I)
TMSK1 (C4I)
TMSK1 (C5I)
TMSK1 (C6I)
TMSK1 (C7I)
TMSK2 (TOI)
PACTL (PAOVI)
PACTL (PAI)
SP0CR1 (SPIE)
SC0CR2
(TIE, TCIE, RIE, ILIE)
SC1CR2
(TIE, TCIE, RIE, ILIE)
ATDxCTL2 (ASCIE)
CRIER (WUPIE)
KWIEG[6:0] and
KWIEH[7:0]
MCCTL (MCZI)
PBCTL (PBOVI)
CRIER (RWRNIE,
TWRNIE,
RERRIE, TERRIE,
BOFFIE, OVRIE)
CRIER (RXFIE)
CTCR (TXEIE[2:0])
PLLCR (LOCKIE, LHIE)
HPRIO Value to
Elevate
–
–
–
–
–
–
$F2
$F0
$EE
$EC
$EA
$E8
$E6
$E4
$E2
$E0
$DE
$DC
$DA
$D8
$D6
$D4
$D2
$D0
$CE
$CC
$CA
$C8
$C6
$C4
$C2
$80–$C0
Technical Data
122
MC68HC912D60A — Rev 3.0
Resets and Interrupts
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