DSP56602 Datasheet, PDF (30/340 Pages) Motorola, Inc – 16-Bit Digital Signal Processor User manual

DSP56602 Overview
DSP56600 Core Description
1.3 DSP56600 CORE DESCRIPTION
The DSP56600 core is based on the DSP56300 core, with a number of power-saving,
performance-enhancing, and cost-reducing features implemented. With its seven-stage
instruction pipeline, the DSP56600 core is capable of executing an instruction on every
clock cycle. A standard interface between the DSP56600 core and the on-chip memory
and peripherals supports many memory and peripheral configurations. Complete
details of the DSP56600 core are provided in the DSP56600 Family Manual
(DSP56600FM/AD).
The following are some of the features of the DSP56600 core:
• 60 Million Instructions Per Second (MIPS) with a 60 MHz clock at 2.7 V
• Fully pipelined 16 × 16-bit parallel Multiplier-Accumulator (MAC)
• 40-bit parallel barrel shifter
• Highly parallel instruction set with unique DSP addressing modes
• Code compatible with the 56300 core
• Position Independent Code (PIC) support
• Nested hardware DO loops
• Fast auto-return interrupts
• On-chip support for software patching and enhancements
• On-chip Phase Lock Loop (PLL)
• Real-time trace capability via External Address Bus
• On-Chip Emulation (OnCE) module
• JTAG port
1.4 DSP56600 CORE FUNCTIONAL BLOCKS
The DSP56600 core provides the following functional blocks:
• Data Arithmetic Logic Unit (Data ALU)
• Address Generation Unit (AGU)
• Program Control Unit (PCU)
• Program Patch Logic
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DSP56602 User’s Manual
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