DSP56602 Datasheet, PDF (136/340 Pages) Motorola, Inc – 16-Bit Digital Signal Processor User manual

Host Interface (HI08)
HI08—External Host Programmer’s Model
provided they have been pre-programmed in the DSP. The HV[6:0] bits are set to $32
(vector location $0064) by hardware, software, individual, and Stop resets.
7.5.2.2
Host Command Bit (HC)—Bit 7
The Host Command (HC) bit is used by the host processor to handshake the execution of
host command interrupts. Normally, the host processor sets HC = 1 to request the host
command interrupt from the DSP core. When the host command interrupt is
acknowledged by the DSP core, the HC bit is cleared by the HI08 hardware. The host
processor can read the state of the HC bit to determine when the host command has been
accepted. After writing HC = 1 to the CVR, the host must not write to the CVR again
until the HC bit is cleared by the HI08 hardware. Setting the HC bit causes host
command pending (HCP) to be set in the HSR. The host can write both the HC and the
HV bits in the same write cycle if desired.
7.5.3 Interface Status Register (ISR)
The Interface Status Register (ISR) is an 8-bit read-only status register used by the host
processor to interrogate the status and flags of the HI08. The host processor can write
this address without affecting the internal state of the HI08, which is useful if the user
desires to access all of the HI08 registers by stepping through the HI08 addresses. The
ISR can be accessed by the DSP core. The status bits are described in the following
paragraphs.
ISR _{7 6}
Interface Status _HR
Register EQ *
Reset = $06
Read/Write
543210
HF3 HF2 TR TX RX
*
DY DE DF
* Indicates reserved bits, read as 0 and should be written with 0 for future compatibility
AA0733
Figure 7-13 Interface Status Register Programming Model
7.5.3.1
Receive Data Register Full (RXDF)—Bit 0
The Receive Data Register Full (RXDF) flag bit indicates that the receive byte registers
(RXH and RXL) contain data from the DSP core and can be read by the host processor.
The RXDF bit is set when the HTX is transferred to the receive byte registers. RXDF is
cleared when the receive data (RXL or RXH according to HLEND bit) register is read by
the host processor. RXDF can be cleared by the host processor using the initialize
function. RXDF may be used to assert the external HREQ pin if the RREQ bit is set.
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DSP56602 User’s Manual
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