MC9S12DB Datasheet, PDF (3/12 Pages) Motorola, Inc – HCS12DB Family Product Proposal

Freescale Semiconductor, Inc.
HCS12DBFAMILYPP/D
Features
• Seven or eight PWM channels with programmable period and duty cycle
– 8-bit 4-channel or 16-bit 2-channel (80-Pin Version)
– 8-bit 8-channel or 16-bit 4-channel (112-Pin Version)
– Separate control for each pulse width and duty cycle
– Center- or left-aligned outputs
– Programmable clock select logic with a wide range of frequencies
• Serial interfaces
– Two asynchronous serial communications interfaces (SCI)
– Up to two synchronous serial peripheral interfaces (SPI)
• Byteflight
– 10 MBit/s serial protocol
• SIM (system integration module)
– CRG (windowed COP watchdog, real-time interrupt, clock monitor,
clock generation and reset)
– MEBI (multiplexed external bus interface)
– MMC (memory map and interface)
– INT (interrupt control)
– BKP (breakpoints)
– BDM (background debug mode)
• Clock generation
– Phase-locked loop clock frequency multiplier
– Limp home mode in absence of external clock
– Slow mode divider
– Low power 0.5 to 40 MHz crystal oscillator reference clock
• Operating frequency
– 50 MHz equivalent to 25 MHz bus speed for single chip
– 40 MHz equivalent to 20 MHz bus speed in expanded bus modes
• Internal 5 V to 2.5 V regulator
• 112-Pin LQFP or 80-Pin QFP package
– I/O lines with 5-V input and drive capability
– 5-V ATD inputs
– Dual supply (5 V for I/O and ATD, 2.5 V for logic
• Development support
– Single-wire background debug™ mode (BDM)
– On-chip hardware breakpoints
MOTOROLA
HCS12DB Family Product Proposal
3
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