MC9S12DB Datasheet, PDF (2/12 Pages) Motorola, Inc – HCS12DB Family Product Proposal

HCS12DBFAMILYPP/D
Freescale Semiconductor, Inc.
Features
NOTE:
Not all features listed here are available in all configurations.
• 16-bit CPU12
– Upward compatible with M68HC11 instruction set
– Interrupt stacking and programmer’s model identical to M68HC11
– 20-bit ALU
– Instruction queue
– Enhanced indexed addressing
• Multiplexed bus
– Single chip or expanded
– 16 address/16 data wide or 16 address/8 data narrow modes
– External address space 1 MB for data and program space (112 pin
package only)
• Wake-up interrupt inputs depending on the package option
– 8-bit port H
– 4-bit port J
– 8-bit port shared with PWM/SPI
• Memory options
– 64K, 128K Byte Flash EEPROM
– 2K Byte EEPROM
– 8K Byte RAM
• One or Two analog-to-digital converters (ATD)
– 1 or 2 times 8-channels, 10-bit resolution depending on the package
option
– External conversion trigger capability
• Up to two 1 M bit per second, CAN 2.0 A, B software compatible
modules
– Five receive and three transmit buffers
– Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or
8 x 8 bit
– Four separate interrupt channels for Rx, Tx, error and wake-up
– Low-pass filter wake-up function
– Loop-back for self test operation
• Enhanced Capture Timer (ECT)
– 16-bit main counter with 7-bit prescaler
– 8 programmable input capture or output compare channels; 4 of the
8 input captures with buffer
– Input capture filters and buffers, three successive captures on four
channels, or two captures on four channels with a capture/compare
selectable on the remaining four
– Four 8-bit or two 16-bit pulse accumulators
– 16-bit modulus down-counter with 4-bit prescaler
– Four user-selectable delay counters for signal filtering
2
HCS12DB Family Product Proposal
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com