MC92300 Datasheet, PDF (3/4 Pages) Motorola, Inc – VITERBI Decoder for Digital TV

Viterbi Decoder Pin Description
R
E
S
VV _E
T TRT
SSE_
PV ^{T TSA}
OET ^{I I} E S
V VNS ^{[ [} T Y
SSI T ^{1 0} _ N
S SDO ^{] ]} NC
OO
VVVV
DDSS
DDSS
T
E
ST
TE
_S
O O MT
O
V V VV O_
VV
DDSS DS
DD
DDSS E E
DD
VDD
OVDD
VC1[2]
OVSS
VC1[1]
OVSS
VC1[0]
OVSS
SYMCLK
OVSS
VSS
VDD
OVDD
VC0[2]
OVSS
VC0[1]
OVSS
VC0[0]
OVSS
OVSS
VSS
VDD
OVDD
VDCLK
OVSS
VDCLK_DIV2
OVSS
VSS
TESTSEL
FREF
TESTOUT
128QFP
VSS
OVSS
OVDD
VDD
VSS
OVSS
BITCLK
OVDD
OVSS
VLCK
OVSS
VO
OVDD
VDD
VSS
OVSS
VFF
OVDD
VEF
OVSS
SR[2]
SR[1]
SR[0]
OVDD
VDD
V V O S SD DOV VODDD DD O VVO
OV
C DV D CS S V S DV S S S SS V SDV
VS
ODD A L A A S S DDA A A AA S SDD
SS
C D [ [ S D[ [ [ [ [ S D
S
T
01
234 56
L
]]
]]] ]]
SYMCLK
BITCLK
VDCLK
VDCLK_DIV2
RESET_N
VLCK
VFF
VEF
SR[2:0]
VO
VC0,VC1[2:0]
SDA
DSA[6:0]
SCL
TESTSEL,
FREF,
TESTOUT,
VCOCTL
- System Clock (input clock)
- System Clock (output clock)
- Input Clock
- VDCLK/2
- Asynchronous Reset
- Viterbi Decoder in Lock
- FIFO Full Flag
- FIFO Empty Flag
- Selected Rate
- Viterbi Decoder Output
- Soft Decision Input
- Data Bus of I²C-interface
- Slave Address of I²C-interface
- Clock Line of I²C-interface
- APLL pins
VTSTI[1:0]
VTSTO
RESET_ASYNC
TEST_SE
TEST_MODE
- Test pins
- Test output
- Teset for Scan Test
- Test pin for Scan Mode
- Test pin for Scan Mode
MOTOROLA Device Test Pins:
51, 56-62, 105, 110-115, 120
(don’t connect these pins)
NOT CONNECTED Pins:
27, 33, 34, 88-94, 99-102
MC92300
Rev.1.3
MOTOROLA
3