MC92300 Datasheet, PDF (1/4 Pages) Motorola, Inc – VITERBI Decoder for Digital TV

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Current [e-mail]/ADC
MC92300
Product Preview
VITERBI Decoder for Digital TV
This product preview describes a high performance device, a Viterbi Decoder, for
Digital-TV applications according to the EBU defined DVB transmission standard for
satellite and cable Set-Top systems.
Viterbi Decoder - Capability Specification
• Operates at max. 50MBits/s output rate to work with all present DVB channels
• Implements K=7, (171₈,133₈) Viterbi decoder for rates 1/2, 2/3, 3/4, 5/6 and 7/8
with a survivor depth of 96
• Code rate and synchronization control programmable via I²C standard serial bus
• Automatic rate selection and signal quality output (qval)
• Full/empty flag generation of input FIFO for system monitoring of VDCLK/BITCLK
ratio
• Simplified system design with internal PLL for the generation of output BITCLK
from the incoming VDCLK for all depuncturing modes
• Available in a 128QFP package
DTVVIT
RESET_N BITCLK
VC0,VC1[2:0] VO
VDCLK
VLCK
SYMCLK
VFF
VTSTI[1:0]
VEF
SR[2:0]
SDA
DSA[6:0]
SCL
Ordering Information
Device
Package
MC92300CG 128QFP
VFF
VEF
VC1[2:0]
Viterbi
VC2[2:0]
Synchronizer
FIFO
Depuncturing
Core
VO
VDCLK
APLL
SYMCLK
RESET_N
VLCK
SR
QVAL
2
VTSTI[1:0]
I²C
Interface
7
SCL DSA SDA
Figure 1. Viterbi Decoder Block Diagram
This document contains information on a new product.
Specifications and information herein are subject to change without notice.
© MOTOROLA, INC. 1997
BIT-
CLK
5/28/97