MC74HC20A Datasheet, PDF (3/5 Pages) ON Semiconductor – Dual 4-Input NAND Gate

MC74HC20A
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Guaranteed Limit}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _Symbol
Parameter
Test Conditions
VCC
V
– 55 to
25_C
v v 85_C
125_C Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VOL
Maximum Low–Level Output
Voltage
v ^{Vin = VIH}
|Iout| 20 µA
2.0
0.1
0.1
0.1
V
4.5
0.1
0.1
0.1
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _6.0
0.1
0.1
0.1
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{v Vin=VIHorVIL |Iout|}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^{v |Iout|}
v |Iout|
2.4 mA
4.0 mA
5.2 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _Iin
Maximum Input Leakage Current Vin = VCC or GND
6.0
± 0.1
± 1.0
± 1.0
µA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _ICC
Maximum Quiescent Supply
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Current (per Package)}
Vin = VCC or GND
Iout = 0 µA
6.0
1
10
40
µA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _Symbol
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _tPLH,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^tPHL
Parameter
Maximum Propagation Delay, Input A, B, or C to Output Y
(Figures 1 and 2)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 2)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _Cin
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ NOTES:
Maximum Input Capacitance
VCC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
—
Guaranteed Limit
v v ^{– 55 to}
25_C
85_C
125_C Unit
90
115
135
ns
45
60
75
18
23
27
15
20
23
75
95
110
ns
30
40
55
15
19
22
13
16
19
10
10
10
pF
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD
Power Dissipation Capacitance (Per Gate)*
26
pF
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
INPUT
A, B, C, OR D
OUTPUT Y
90%
50%
10%
tf
tPLH
90%
50%
10%
tTLH
tr
VCC
GND
tPHL
tTHL
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
CL*
* Includes all probe and jig capacitance
Figure 2. Test Circuit
A
Figure 1. Switching Waveforms
B
Y
C
D
EXPANDED LOGIC DIAGRAM
(1/2 OF THE DEVICE)
High–Speed CMOS Logic Data
3
DL129 — Rev 6
MOTOROLA