MC74F803 Datasheet, PDF (3/5 Pages) Motorola, Inc – CLOCK DRIVER QUAD D-TYPE FLIP-FLOP WITH MATCHED PROPAGATION DELAYS

MC74F803
AC OPERATING REQUIREMENTS (TA = 0 to 70°C, VCC = 5.0 V ± 10%)
Symbol
Parameter
CL = 50 pF
CL = 100 pF
Min
Max
Min
Max
Unit
ts(H)
ts(L)
Setup Time, HIGH or LOW
Dn to CP
3.0
—
4.0
—
ns
3.0
—
4.0
—
tf
tp + ts (see Note)
—
9.0
—
12
ns
th(H)
th(L)
Hold Time, HIGH or LOW
Dn to CP
2.0
—
2.0
—
ns
2.0
—
2.0
—
tw(H)
tw(L)
CP Pulse Width
HIGH or LOW
7.0
—
8.0
—
ns
6.0
—
8.0
—
The combination of the setup time (ts) requirement and maximum propagation delay (tp) are guaranteed to be within this limit for all conditions.
APPLICATION NOTE
The closely matched outputs of the MC74F803 provide an ideal interface for the clock input of Motorola’s high-frequency
microprocessors.
74F803 INTERFACE AS CLOCK TO MC68020 SYSTEM
MC68020/MC68030
E1 _CLK
VCC
74F04
1
2
14
MC74F803
4 _D0
O0 ³
5 _D1
10 _D2
11 _D3
1
O1 ⁶
O2 ⁹
O3 ¹²
CP
7
8
CLK
66 MHz
33CLK1
MC68881/MC68882
C2 _CLK
33CLK2 (40 mA OUTPUT DRIVE)
33CLK
VCC
RU
RT
TIMING SOLUTIONS
BR1333 — REV 4
MOTOROLA
3