MC54HC154 Datasheet, PDF (3/7 Pages) Motorola, Inc – 1-of-16 Decoder/Demultiplexer High-Performance Silicon-Gate CMOS

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _Symbol
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _tPLH,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _tPHL
Parameter
Maximum Propagation Delay, Input A to Output Y
(Figures 1 and 3)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPLH,
tPHL
Maximum Propagation Delay, CS to Output Y
(Figures 2 and 3)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _tTLH,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^tTHL
Maximum Output Transition Time, Any Output
(Figures 2 and 3)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _Cin
Maximum Input Capacitance
MC54/74HC154
VCC
V
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
—
Guaranteed Limit
v v ^{– 55 to}
25_C
85_C
125_C Unit
190
240
285
ns
38
48
57
32
41
48
175
220
265
ns
35
44
53
30
37
45
75
95
110
ns
15
19
22
13
16
19
10
10
10
pF
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD
Power Dissipation Capacitance (Per Package)*
80
pF
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
PIN DESCRIPTIONS
INPUTS
A0, A1, A2, A3 (Pins 23, 22, 21, 20)
Address inputs. These inputs, when the 1–of–16 decoder
is enabled, determine which of its sixteen active–low outputs
is selected.
OUTPUTS
Y0 – Y15 (Pins 1 – 11, 13 – 17)
Active–low outputs. These outputs assume a low level
when addressed and both chip–select inputs are active.
These outputs remain high when not addressed or a chip–
select input is high.
CONTROL INPUTS
CS1, CS2 (Pins 18, 19)
Active–low chip–select inputs. With low levels on both of
these inputs, the outputs of the decoder follow the Address
inputs. A high level on either input forces all outputs high.
Inputs
CS1 CS2 A3 A2 A1 A0 Y0 Y1
L
L LLLLLH
L
L L L LHHL
L
L L LHLHH
L
L L LHHHH
L
L LHL LHH
L
L LHLHHH
L
L LHHLHH
L
L LHHHHH
L
L HL L LHH
L
L HL LHHH
L
L HLHLHH
L
L HLHHHH
L
L HHL LHH
L
L HHLHHH
L
L HHHLHH
L
L HHHHHH
L
H XXXXHH
H
L XXXXHH
H
H XXXXHH
H = High Level, L = Low Level, X = Don’t Care
FUNCTION TABLE
Y2 Y3 Y4 Y5 Y6
HHHHH
HHHHH
L HHHH
H L HHH
HH L HH
HHH L H
HHHH L
HHHHH
HHHHH
HHHHH
HHHHH
HHHHH
HHHHH
HHHHH
HHHHH
HHHHH
HHHHH
HHHHH
HHHHH
Outputs
Y7 Y8
HH
HH
HH
HH
HH
HH
HH
LH
HL
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
Y9 Y10 Y11 Y12 Y13 Y14 Y15
HHHHHHH
HHHHHHH
HHHHHHH
HHHHHHH
HHHHHHH
HHHHHHH
HHHHHHH
HHHHHHH
HHHHHHH
LHHHHHH
HL HHHHH
HH L HHHH
HHH L HHH
HHHH L HH
HHHHH L H
HHHHHH L
HHHHHHH
HHHHHHH
HHHHHHH
High–Speed CMOS Logic Data
3
DL129 — Rev 6
MOTOROLA