MC54HC154 Datasheet, PDF (1/7 Pages) Motorola, Inc – 1-of-16 Decoder/Demultiplexer High-Performance Silicon-Gate CMOS

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
1-of-16 Decoder/Demultiplexer
High–Performance Silicon–Gate CMOS
The MC54/74HC154 is identical in pinout to the LS154. The device inputs
are compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
This device, when enabled, selects one of 16 active–low outputs. Two
active–low Chip Selects are provided to facilitate the chip–select, demulti-
plexing, and cascading functions. When either Chip Select is high, all
outputs are high. The demultiplexing function is accomplished by using the
Address inputs to select the desired device output. Then, while holding one
chip select input low, data can be applied to the other chip select input (see
Application Note).
The HC154 is primarily used for memory address decoding and data
routing applications.
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 192 FETs or 48 Equivalent Gates
MC54/74HC154
24
1
J SUFFIX
CERAMIC PACKAGE
CASE 758–02
24
1
24
1
N SUFFIX
PLASTIC PACKAGE
CASE 724–03
DW SUFFIX
SOIC PACKAGE
CASE 751E–04
ORDERING INFORMATION
MC54HCXXXJ
MC74HCXXXN
MC74HCXXXDW
Ceramic
Plastic
SOIC
LOGIC DIAGRAM
BINARY
ADDRESS
INPUTS
A0 ²³
A1 ²²
A2 ²¹
A3 ²⁰
CHIP
SELECT
INPUTS
18
CS1
CS2 ¹⁹
1 _Y0
2 _Y1
3 _Y2
4 _Y3
5 _Y4
6 _Y5
7 _Y6
8 _Y7
9 _Y8
10 _Y9
11 _Y10
13 _Y11
14 _Y12
15 _Y13
16 _Y14
17 _Y15
ACTIVE–LOW
OUTPUTS
PIN 24 = VCC
PIN 12 = GND
PIN ASSIGNMENT
Y0 1
Y1 2
Y2 3
Y3 4
Y4 5
Y5 6
Y6 7
Y7 8
Y8 9
Y9 10
Y10 11
GND 12
24 VCC
23 A0
22 A1
21 A2
20 A3
19 CS2
18 CS1
17 Y15
16 Y14
15 Y13
14 Y12
13 Y11
10/95
© Motorola, Inc. 1995
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