MC14530B Datasheet, PDF (3/7 Pages) Motorola, Inc – DUAL 5-INPUT MAJORITY LOGIC GATE

ÎÎÎÎ_SÎÎÎÎ_WIÎÎÎÎ_TCHÎÎÎÎ_INGÎÎÎÎ_CHÎÎÎÎ_ARÎÎÎÎ_AChCaÎÎÎÎ_TrEacRtÎÎÎÎ_eISriTsÎÎÎÎ_tIiCcSÎÎÎÎ_{* (C}ÎÎÎÎ_L=5ÎÎÎÎ_0pFÎÎÎÎ_,TAÎÎÎÎ₌₂ÎÎÎÎ_{5_C}ÎÎÎÎ_)SymÎÎÎÎ_bolÎÎÎÎÎÎÎÎ_VÎÎÎÎ_DDÎÎÎÎÎÎÎÎÎÎÎÎ_MinÎÎÎÎÎÎÎÎ_TÎÎÎÎ_ypÎÎÎÎ_# ÎÎÎÎÎÎÎÎ_MaxÎÎÎÎÎÎÎÎ_UÎÎÎÎ_nitÎÎÎÎ
Output Rise and Fall Time
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
tTLH,
ns
tTHL
5.0
—
100
200
10
—
50
100
15
—
40
80
Propagation Delay Time
A, C, W = VDD; B, E = Gnd; D = Pulse Generator
tPLH = (1.7 ns/pF) CL + 290 ns
tPLH = (0.66 ns/pF) CL + 127 ns
tPLH = (0.5 ns/pF) CL + 85 ns
tPLH
ns
5.0
—
375
960
10
—
160
400
15
—
110
300
tPHL = (1.7 ns/pF) CL + 345 ns
tPHL = (0.66 ns/pF) CL + 162 ns
tPHL = (0.5 ns/pF) CL + 95 ns
tPHL
5.0
—
430
1200
ns
10
—
195
540
15
—
120
410
A, B, C, D, E = Pulse Generator; W = VDD
tPLH = (1.7 ns/pF) CL + 170 ns
tPLH = (0.66 ns/pF) CL + 87 ns
tPLH = (0.5 ns/pF) CL + 60 ns
tPLH
ns
5.0
—
255
640
10
—
120
300
15
—
86
210
tPHL = (1.7 ns/pF) CL + 195 ns
tPHL = (0.66 ns/pF) CL + 92 ns
tPHL = (0.5 ns/pF) CL + 75 ns
tPHL
5.0
—
280
750
ns
10
—
125
330
15
—
100
250
A, B, C, D, E = Gnd; W = Pulse Generator
tPHL, tPLH = (1.7 ns/pF) CL + 145 ns
tPHL, tPLH = (0.66 ns/pF) CL + 72 ns
tPHL, tPLH = (0.5 ns/pF) CL + 50 ns
tPLH,
ns
tPHL
5.0
—
230
575
10
—
105
265
15
—
75
190
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
VDD
16
PULSE
GENERATOR
A
B
Z
C
D
E
CL
W
A
B
C
Z
D
E
W
CL
20 ns
20 ns
8 VSS
VDD
Vin
50%
DUTY
VSS
CYCLE
Figure 1. Power Dissipation Test
Circuit and Waveform
MOTOROLA CMOS LOGIC DATA
MC14530B
3