MC14530B Datasheet, PDF (1/7 Pages) Motorola, Inc – DUAL 5-INPUT MAJORITY LOGIC GATE

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Dual 5-Input Majority
Logic Gate
The MC14530B dual five–input majority logic gate is constructed with
P–channel and N–channel enhancement mode devices in a single
monolithic structure. Combinational and sequential logic expressions are
easily implemented with the majority logic gate, often resulting in fewer
components than obtainable with the more basic gates. This device can also
provide numerous logic functions by using the W and some of the logic (A
thru E) inputs as control inputs.
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ • Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{MAXIMUM RATINGS* (Voltages Referenced to VSS)}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Symbol
Parameter
Value
Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^{VDD DC Supply Voltage}
– 0.5 to + 18.0
V
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^{Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V}
Iin, Iout Input or Output Current (DC or Transient),
± 10
mA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{per Pin}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{PD Power Dissipation, per Packageâ€} 
500
mW
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Tstg Storage Temperature}
– 65 to + 150
_C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _TL
Lead Temperature (8–Second Soldering)
260
_C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ * Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
LOGIC TABLE
INPUTS A B C D E
W
Z
For all combinations of inputs where three or
0
1
more inputs are logical “0”.
1
0
For all combinations of inputs where three or
0
0
more inputs are logical “1”.
1
1
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open.
REV 3
1/94
©MMOotoTrOolaR, IOncL. A199C5MOS LOGIC DATA
MC14530B
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
TA = – 55° to 125°C for all packages.
W ^{BLOCK DIAGRAM}
6
1
A
2
B
7
3
C
M5
Z
4
D
5
E
 * Z = M5
 Z = M5
  Z = M5
W = (ABC+ABD+ABE+ACD+
W = (ACE+ADE+BCD+BCE+
W = (BDE+CDE) W
9
A
10
B
11
C
M5
12
D
15
Z
13
E
14
W
* M5 is a logical “1” if any three or more
inputs are logical “1”.
   Exclusive NOR Exclusive OR
TRUTH TABLE
M5 W Z
001
010
100
111
VDD = PIN 16
VSS = PIN 8
MC14530B
1