56F807 Datasheet, PDF (28/52 Pages) Motorola, Inc – 56F807 16-bit Hybrid Processor

Freescale Semiconductor, Inc.
Table 29. External Bus Asynchronous Timing^1,2 (Continued)
Operating Conditions: V_SS = V_SSA = 0 V, V_DD = V_DDA = 3.0–3.6 V, T_A = –40° to +85°C, C_L ≤ 50pF, f_op = 80MHz
Characteristic
Symbol
Min
Max
Unit
Address Valid to Input Data Valid
Wait states = 0
Wait states > 0
t_AD
—
—
1
ns
(T*WS)+1
ns
Address Valid to RD Asserted
t_ARDA
-4.4
—
ns
RD Asserted to Input Data Valid
Wait states = 0
Wait states > 0
t_RDD
—
2.4
ns
—
(T*WS) + 2.4
ns
WR Deasserted to RD Asserted
t_WRRD
6.8
—
ns
RD Deasserted to RD Asserted
t_RDRD
0
—
ns
WR Deasserted to WR Asserted
t_WRWR
14.1
—
ns
RD Deasserted to WR Asserted
t_RDWR
12.8
—
ns
1. Timing is both wait state and frequency dependent. In the formulas listed, WS = the number of wait states and
T = Clock Period. For 80MHz operation, T = 12.5ns.
2. Parameters listed are guaranteed by design.
To calculate the required access time for an external memory for any frequency < 80MHz, use this formula:
Top = Clock period @ desired operating frequency
WS = Number of wait states
Memory Access Time = (Top*WS) + (Top- 11.5)
A0–A15,
PS, DS
(See Note)
RD
WR
D0–D15
t_AWR
t_WRWR
t_ARDA
t_WR
t_WRRD
t_ARDD
t_RD
t_RDA
t_RDRD
t_RDWR
t_WRD
t_DOS
Data Out
t_AD
t_DOH
t_RDD
Data In
t_DRD
Note: During read-modify-write instructions and internal instructions, the address lines do not change state.
Figure 13. External Bus Asynchronous Timing
28
56F807 Technical Data
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